;======= ;screech id: 2004 ; ; ;garzol ;search: 36A LBL CYS DIA DIB DOA 04F B<=04F LBL 005 IOL F ;search: ADCSK ADSK trigger LBL 007 ;======= ;switch matrix ;DIA calls: 011, 7F2: (selftest of coils) ;DOA calls: 00E (BL should contains the current Acc), 7EF: (selftest of coils) send #A ;DIB no call. ;SN7445: ;bcd demux ;pins 1 2 3 4 5 6 7 9 10 11 ;for 0 1 2 3 4 5 6 7 8 9 ; ;pins 15 14 13 12 ;for A B C D ;======= ;We observed that device 0x4 (IOL 41) controls RAMCMOS HM6508 ;Hence: ;IO device numbers: ;0x4: A2361 (aka A1761-13) ;0x2: A2362 (aka A1762-13) ;======== ;Considerations about the 11696 ;IO01 pin19 reg#F coil #F ;IO02 pin20 reg#E coil #E ;IO03 pin24 reg#D coil #D ;IO04 pin25 reg#C coil #C ; ;IO05 pin26 reg#B coil #B ;IO06 pin27 reg#A coil #A ;IO07 pin28 reg#9 coil #9 ;IO08 pin29 reg#8 coil #8 ; ;IO09 pin30 reg#7 coil ball home (group C, bit-1, IOL D6/DB, Acc=7) ;IO10 pin31 reg#6 coil knocker (group C, bit-2, IOL D6/DB, Acc=6) ; ;IO11 pin32 not used (Buffer A6, pin 5->4 not used) ;; 33, 34, 35, 37, 38 ;; IO12, IO13, IO14, IO15, IO16 Group C-4, Group D ;; for sound control ; ;;so called group 7? ;IO17 pin39 reg61 bit A bonus ;IO18 pin40 reg62 bit B bonus ;IO19 pin41 reg64 bit C bonus ;IO20 pin42 reg68 bit D bonus ; ;IO21 pin18 reg#71 lite special ;IO22 pin17 reg#72 lite extra ball ;IO23 pin16 reg#74 lite double bonus ;IO24 pin15 reg#78 play signal (with a link to port PC9) ; ;play signal will be updated thru D5, Acc=b1xxx ;used opcodes are: ;IOL Dx, x is anything but E, 7 ; ;IOL D0, on entry 3 | C ;IOL D1, used only once in selftest ;IOL DB, return value is never read. called 16 times in a row. Why? ;IOL D6, return value is not read. used 8 times. Set 1 bit =f(A). see 11696 table for more info ;IOL D6, to be used to set 1 output to 1, leaving all the others unchanged, Acc determines which bit to be set ;IOL D6/DB, for modifying 1 bit in group ABCD, (not E or F) ;IOL D7 ? ==> never used ;IOL DB, is the opposite of D6 (bit reset) ;IOL D3 ==> play tone. Value in A determine height ;IOL D2 is used only once in the self test (710) ;and once in 2F0 ; ;IOL D0 is only used for seltest in main rom, ;or only in game prom. ; ;IOL D1/D9 are only used for seltest. Nowhere else ;IOL DC/DD are only used for seltest. Nowhere else ;IOL D0: coil C/D/E/F ;IOL D1: coil 8/9/A/B ;IOL D2: coil 7/6/NC/Tone D (ball home, knocker) ;IOL D3: tone C/B/A/On-off ;IOL D4: Lamp L61/62/64/68 ;IOL D5: Lamp L71/72/74/play signal ;==== ;The 11696 autotest does ;IOL D0/D8: check group A ;IOL D1/D9: check group B ;IOL D2/DA: check group C ;IOL D3/DF: check group D ;IOL D4/DC: check group E ;IOL D5/DD: check group F ;======== ;3bits =>ball1..5, gover, (bits DA1..3) ;4th bit=>tilt (bit DA4) ;are controlled by DA1..3, >DA4 of 10788 (via latch+bcd decoder) ;latch sig is XB0 ;======== ;match number controlled through latch+bcd decoder ;controlled by DA1..4 ;latch sig is XB1 ;======== ;boot 000 81 T 001 ; Transfer 001 26 RF1 ; Reset FF1 002 25 RF2 ; Reset FF2 003 56 C0 TL 6C0 ; Transfer Long ;(99, 89)<-#A0 ;loop0: ;x<-9 ;loop1: ; ;Cx<-DIA(strobe9) ;if X(n)<>X(n-1) ; DxA 012 3F EX 0 ; Exchange Accumulator and Memory 013 0C EOR ; Logical Exclusive-OR 014 1E SKZ ; Skip on Accumulator Zero ;if (statex)(n) != (statex)(n-1) goto label20 015 A0 T 020 ; Transfer ;nothing changed on strobe x ;B was Cx, then LD 1 changed it to Dx 016 36 LD 1 ; Load Accumulator from Memory 017 7E LDI 1 ; Load Accumulator Immediate 018 09 ADSK ; Add and skip on carry-out ;if (Dx)+1 <=#F goto label22 019 A2 T 022 ; Transfer ; (Dx) > #F 01A 3E EX 1 ; (Dx)<-#0, BL<-#Cx 01B 35 LD 2 ; A<-(Cx), BL<-#Ex 01C 0C EOR ; Logical Exclusive-OR 01D 1E SKZ ; Skip if (Cx)==(Ex) ;if (Cx)!=(Ex) goto label26 01E A6 T 026 ; Transfer ; (Cx)==(Ex) 01F 35 LD 2 ; BL<-#Cx ;label20: ;change on row x of switch matrix,(Here B is always 0Cx) 020 34 LD 3 ; BL<-#Fx 021 35 LD 2 ; A<-(Fx), B<-#Dx ;label22: 022 2E EXD 1 ; (Dx)<-(Fx), BM<-#C, BL-- while (x>=0) goto label0D 023 8D T 00D ; Transfer ;all lines scanned from 9..0 024 50 80 TL 080 ; Transfer Long ;label26: ( Here, B=Ex, A=(Cx) xor (Ex) ), A=xyzt with 1 if change from t-1 to t or 0 otherwise 026 0E COMP ; Complement A, /((Cx) xor (Ex)) -> if no diff: 1, if diff: 0 027 0D AND ; Logical AND, /((Cx) xor (Ex)) and (Ex) -> 1 if Ex(b)=1 and no diff 028 3D EX 2 ; (Ex)<-> /((Cx) xor (Ex)) and (Ex), B<-Cx -> A<-(Ex) 029 0E COMP ; Complement A, A<-/(Ex)old 02A 0D AND ; Logical AND, A<- /(Ex)old and (Cx) 02B 1E SKZ ; Skip on Accumulator Zero 02C AE T 02E ; Transfer 02D A0 T 020 ; Transfer to decrement x and goto 00D 02E 3F EX 0 ; Exchange Accumulator and Memory 02F 1B LXA ; Load X Register from Accumulator 030 77 LDI 8 ; Load Accumulator Immediate 031 0D AND ; Logical AND 032 1E SKZ ; Skip on Accumulator Zero 033 BD T 03D ; Transfer 034 7B LDI 4 ; Load Accumulator Immediate 035 0D AND ; Logical AND 036 1E SKZ ; Skip on Accumulator Zero 037 BD T 03D ; Transfer 038 7D LDI 2 ; Load Accumulator Immediate 039 0D AND ; Logical AND 03A 1E SKZ ; Skip on Accumulator Zero 03B BD T 03D ; Transfer 03C 7E LDI 1 ; Load Accumulator Immediate 03D 50 40 TL 040 ; Transfer Long 03F 91 T 011 ; Transfer 040 1A XAX ; Exchange Accumulator and X 041 3D EX 2 ; Exchange Accumulator and Memory 042 11 LABL ; Load Accumulator with BL 043 67 ADI 8 ; Add Immediate and skip on carry-out 044 86 T 046 ; Transfer 045 8B T 04B ; Transfer 046 16 SKF1 ; Skip if FF1 Equals 1 047 89 T 049 ; Transfer 048 8B T 04B ; Transfer 049 6D ADI 2 ; Add Immediate and skip on carry-out 04A B9 T 079 ; Transfer 04B 12 LAX ; Load Accumulator from X Register 04C 0F OR ; Logical OR 04D 3D EX 2 ; Exchange Accumulator and Memory 04E 12 LAX ; Load Accumulator from X Register 04F 0E COMP ; Complement 050 6B ADI 4 ; Add Immediate and skip on carry-out 051 6E ADI 1 ; Add Immediate and skip on carry-out 052 93 T 053 ; Transfer 053 67 ADI 8 ; Add Immediate and skip on carry-out 054 62 ADI D ; Add Immediate and skip on carry-out 055 96 T 056 ; Transfer 056 1B LXA ; Load X Register from Accumulator 057 19 XABL ; Exchange Accumulator and BL 058 00 F0 LBL 00F ; Load B Long 05A 3F EX 0 ; Exchange Accumulator and Memory 05B 37 LD 0 ; Load Accumulator from Memory 05C 09 ADSK ; Add and skip on carry-out 05D AC T 06C ; Transfer 05E 1A XAX ; Exchange Accumulator and X 05F 3F EX 0 ; Exchange Accumulator and Memory 060 37 LD 0 ; Load Accumulator from Memory 061 0B AD ; Add 062 3F EX 0 ; Exchange Accumulator and Memory 063 1A XAX ; Exchange Accumulator and X 064 1E SKZ ; Skip on Accumulator Zero 065 7F LDI 0 ; Load Accumulator Immediate 066 77 LDI 8 ; Load Accumulator Immediate 067 0B AD ; Add 068 1A XAX ; Exchange Accumulator and X 069 70 LDI F ; Load Accumulator Immediate 06A 1A XAX ; Exchange Accumulator and X 06B AE T 06E ; Transfer 06C 14 SKF2 ; Skip if FF2 Equals 1 06D BB T 07B ; Transfer 06E 0E COMP ; Complement 06F 06 XS ; Exchange SA and SB 070 6F CYS ; Cycle SA register and Accumulator 071 12 LAX ; Load Accumulator from X Register 072 6F CYS ; Cycle SA register and Accumulator 073 12 LAX ; Load Accumulator from X Register 074 6E ADI 1 ; Add Immediate and skip on carry-out 075 78 LDI 7 ; Load Accumulator Immediate 076 75 LDI A ; Load Accumulator Immediate 077 6F CYS ; Cycle SA register and Accumulator 078 05 RTN ; Return 079 50 1F TL 01F ; Transfer Long 07B 50 0B TL 00B ; Transfer Long 07D BE T 07E ; Transfer 07E 50 11 TL 011 ; Transfer Long ;All lines scanned from 9 down to 0 080 7E LDI 1 ; Load Accumulator Immediate 081 00 76 LBL 089 ; Load B Long 083 09 ADSK ; Add and skip on carry-out 084 94 T 094 ; Transfer 085 3E EX 1 ; Exchange Accumulator and Memory 086 7E LDI 1 ; Load Accumulator Immediate 087 09 ADSK ; Add and skip on carry-out 088 94 T 094 ; Transfer ;(89, 99) reached 0 089 75 LDI A ; Load Accumulator Immediate 08A 3C EX 3 ; Exchange Accumulator and Memory 08B 7E LDI 1 ; Load Accumulator Immediate 08C 09 ADSK ; Add and skip on carry-out 08D 91 T 091 ; Transfer 08E 3E EX 1 ; Exchange Accumulator and Memory 08F 7E LDI 1 ; Load Accumulator Immediate 090 0B AD ; Add 091 3F EX 0 ; Exchange Accumulator and Memory 092 56 76 TL 676 ; Transfer Long ;save (89,99)++ 094 3F EX 0 ; Exchange Accumulator and Memory 095 00 76 LBL 089 ; Load B Long 097 36 LD 1 ; Load Accumulator from Memory 098 1E SKZ ; Skip on Accumulator Zero 099 BA T 0BA ; Transfer to 00B (via 0BA:TL 00B) 09A 7C LDI 3 ; Load Accumulator Immediate 09B 0B AD ; Add 09C 1E SKZ ; Skip on Accumulator Zero 09D BA T 0BA ; Transfer to 00B (via 0BA:TL 00B) ;99+#3=0 donc 99 contenait #D ;reset all lines of group ABCD 09E 7F LDI 0 ; Load Accumulator Immediate 09F 1B LXA ; Load X Register from Accumulator 0A0 1C DB IOL DB ; Input/Output Long 0A2 12 LAX ; Load Accumulator from X Register 0A3 6E ADI 1 ; Add Immediate and skip on carry-out 0A4 9F T 09F ; Transfer 0A5 14 SKF2 ; Skip if FF2 Equals 1 0A6 AE T 0AE ; Transfer 0A7 00 B6 LBL 049 ; Load B Long 0A9 78 LDI 7 ; Load Accumulator Immediate 0AA 09 ADSK ; Add and skip on carry-out 0AB 65 DC ; Decimal Correction 0AC 3F EX 0 ; Exchange Accumulator and Memory 0AD BC T 0BC ; Transfer 0AE 16 SKF1 ; Skip if FF1 Equals 1 0AF B1 T 0B1 ; Transfer 0B0 BC T 0BC ; Transfer 0B1 00 BD LBL 042 ; Load B Long 0B3 7E LDI 1 ; Load Accumulator Immediate 0B4 0D AND ; Logical AND 0B5 1E SKZ ; Skip on Accumulator Zero 0B6 B8 T 0B8 ; Transfer 0B7 AD T 0AD ; Transfer 0B8 54 87 TL 487 ; Transfer Long 0BA 50 0B TL 00B ; Transfer Long 0BC 56 14 TL 614 ; Transfer Long 0BE 00 00 LBL 0FF ; Load B Long ;beginning of table for LB 0C0 B7 T 0F7 ; Transfer 0C1 16 SKF1 ; Skip if FF1 Equals 1 0C2 AE T 0EE ; Transfer 0C3 BF T 0FF ; Transfer 0C4 BE T 0FE ; Transfer 0C5 4E SKBI E ; Skip if BL equals to Immediate. 0C6 EA TM (EA) (target addr=163) ; Transfer and Mark Indirect 0C7 1F DECB ; Decrement BL 0C8 BD T 0FD ; Transfer 0C9 B5 T 0F5 ; Transfer 0CA A5 T 0E5 ; Transfer 0CB AD T 0ED ; Transfer 0CC 46 SKBI 6 ; Skip if BL equals to Immediate. 0CD A6 T 0E6 ; Transfer 0CE E9 TM (E9) (target addr=162) ; Transfer and Mark Indirect 0CF E8 TM (E8) (target addr=161) ; Transfer and Mark Indirect ;beginning of table for TM 0D0 17 INCB ; Increment BL 0D1 18 XBMX ; Exchange BM and X 0D2 22 SF1 ; Set FF1 0D3 23 DIB ; Discrete Input Group B 0D4 2D EXD 2 ; Exchange Accumulator and Memory and decrement BL 0D5 2E EXD 1 ; Exchange Accumulator and Memory and decrement BL 0D6 7B LDI 4 ; Load Accumulator Immediate 0D7 5C 40 TL C40 ; Transfer Long 0D9 41 SKBI 1 ; Skip if BL equals to Immediate. 0DA 42 SKBI 2 ; Skip if BL equals to Immediate. 0DB 43 SKBI 3 ; Skip if BL equals to Immediate. 0DC 49 SKBI 9 ; Skip if BL equals to Immediate. 0DD 4A SKBI A ; Skip if BL equals to Immediate. 0DE 4B SKBI B ; Skip if BL equals to Immediate. 0DF 4C SKBI C ; Skip if BL equals to Immediate. 0E0 80 T 0C0 ; Transfer 0E1 81 T 0C1 ; Transfer 0E2 82 T 0C2 ; Transfer 0E3 83 T 0C3 ; Transfer 0E4 51 52 TL 152 ; Transfer Long 0E6 53 54 TL 354 ; Transfer Long 0E8 61 ADI E ; Add Immediate and skip on carry-out 0E9 62 ADI D ; Add Immediate and skip on carry-out 0EA 63 ADI C ; Add Immediate and skip on carry-out 0EB 64 ADI B ; Add Immediate and skip on carry-out 0EC 69 ADI 6 ; Add Immediate and skip on carry-out 0ED 6A ADI 5 ; Add Immediate and skip on carry-out 0EE 6B ADI 4 ; Add Immediate and skip on carry-out 0EF 6C ADI 3 ; Add Immediate and skip on carry-out 0F0 71 LDI E ; Load Accumulator Immediate 0F1 72 LDI D ; Load Accumulator Immediate 0F2 73 LDI C ; Load Accumulator Immediate 0F3 74 LDI B ; Load Accumulator Immediate 0F4 91 T 0D1 ; Transfer 0F5 92 T 0D2 ; Transfer 0F6 93 T 0D3 ; Transfer 0F7 94 T 0D4 ; Transfer 0F8 99 T 0D9 ; Transfer 0F9 B5 T 0F5 ; Transfer 0FA B7 T 0F7 ; Transfer 0FB AC T 0EC ; Transfer 0FC 9D T 0DD ; Transfer 0FD B9 T 0F9 ; Transfer 0FE BB T 0FB ; Transfer 0FF AE T 0EE ; Transfer ;end of table for TM ;set FF1 and goto 005 100 22 SF1 ; Set FF1 101 50 05 TL 005 ; Transfer Long ;reset FF1 and goto 005 103 26 RF1 ; Reset FF1 104 81 T 101 ; Transfer ;loop forever 105 C0 LB (C0) (B<=048) 106 0F OR 107 3F EX 0 108 25 RF2 ; Reset FF2 109 CF LB (CF) (B<=017) 10A C0 LB (C0) (B<=048) 10B 78 LDI 7 10C 0D AND 10D 3F EX 0 10E 01 00 TML 100 ; Transfer and Mark Long 110 8E T 10E ; Transfer 111 CF LB (CF) (B<=017) 112 77 LDI 8 113 0F OR 114 3F EX 0 ; Exchange Accumulator and Memory 115 21 SF2 ; Set FF2 116 8A T 10A ; Transfer ;subroutine mem(@B)++ max to 0xF ;do nothing if FF1==0 117 7E LDI 1 ; Load Accumulator Immediate 118 24 RC ; Reset Carry flip-flop 119 16 SKF1 ; Skip if FF1 Equals 1 11A 05 RTN ; Return 11B 0B AD ; Add 11C 3F EX 0 ; Exchange Accumulator and Memory 11D 15 SKC ; Skip on Carry flip-flop 11E 05 RTN ; Return 11F 70 LDI F ; Load Accumulator Immediate 120 3F EX 0 ; Exchange Accumulator and Memory 121 07 RTNSK ; Return and Skip ;subroutine mem(@B)++ in BCD mode ;rtn or rtnsk whether result >=10 or not 122 7E LDI 1 ; Load Accumulator Immediate 123 24 RC ; Reset Carry flip-flop 124 16 SKF1 ; Skip if FF1 Equals 1 125 A6 T 126 ; Transfer 126 69 ADI 6 ; Add Immediate and skip on carry-out 127 09 ADSK ; Add and skip on carry-out 128 65 DC ; Decimal Correction 129 3F EX 0 ; Exchange Accumulator and Memory 12A 15 SKC ; Skip on Carry flip-flop 12B 05 RTN ; Return 12C 07 RTNSK ; Return and Skip ;subroutine ;B is loaded with one of AB B3 A3 83 9B 8B 12D 7E LDI 1 ; Load Accumulator Immediate 12E 1B LXA ; Load X Register from Accumulator 12F 24 RC ; Reset Carry flip-flop 130 69 ADI 6 ; Add Immediate and skip on carry-out 131 09 ADSK ; Add and skip on carry-out 132 65 DC ; Decimal Correction 133 3F EX 0 ; Exchange Accumulator and Memory 134 15 SKC ; Skip on Carry flip-flop 135 BC T 13C ; Transfer 136 7E LDI 1 ; Load Accumulator Immediate 137 17 INCB ; Increment BL 138 BA T 13A ; Transfer 139 BC T 13C ; Transfer 13A 48 SKBI 8 ; Skip if BL equals to Immediate. 13B AF T 12F ; Transfer 13C 12 LAX ; Load Accumulator from X Register 13D 05 RTN ; Return ;subroutine. Follow up in 5B1 ;IO(1) of dev 40 (Data In) reset, and IO(3) of dev 40 (/WE) set then reset ;to its previous value 13E 55 B1 TL 5B1 ; Transfer Long ;bit set in memory at @(B reg) only if FF1 is 1 140 7E LDI 1 ; Load Accumulator Immediate 141 7D LDI 2 ; Load Accumulator Immediate 142 7B LDI 4 ; Load Accumulator Immediate 143 77 LDI 8 ; Load Accumulator Immediate 144 16 SKF1 ; Skip if FF1 Equals 1 145 05 RTN ; Return 146 0F OR ; Logical OR 147 3F EX 0 ; Exchange Accumulator and Memory 148 05 RTN ; Return ;bit reset in memory at @(B reg) only if FF1 is 1 149 71 LDI E ; Load Accumulator Immediate 14A 72 LDI D ; Load Accumulator Immediate 14B 74 LDI B ; Load Accumulator Immediate 14C 78 LDI 7 ; Load Accumulator Immediate 14D 16 SKF1 ; Skip if FF1 Equals 1 14E 05 RTN ; Return 14F 0D AND ; Logical AND 150 87 T 147 ; Transfer ;reset FF1 if bit x of mem(@B) is 0 151 7E LDI 1 ; Load Accumulator Immediate 152 7D LDI 2 ; Load Accumulator Immediate 153 7B LDI 4 ; Load Accumulator Immediate 154 77 LDI 8 ; Load Accumulator Immediate 155 16 SKF1 ; Skip if FF1 Equals 1 156 05 RTN ; Return 157 0D AND ; Logical AND 158 1E SKZ ; Skip on Accumulator Zero 159 05 RTN ; Return 15A 26 RF1 ; Reset FF1 15B 05 RTN ; Return ;toggle FF1 15C 16 SKF1 ; Skip if FF1 Equals 1 15D 9F T 15F ; Transfer 15E 9A T 15A ; Transfer 15F 22 SF1 ; Set FF1 160 05 RTN ; Return ;set FF1 if bit x of mem(@B) is set 161 7E LDI 1 ; Load Accumulator Immediate 162 7D LDI 2 ; Load Accumulator Immediate 163 7B LDI 4 ; Load Accumulator Immediate 164 77 LDI 8 ; Load Accumulator Immediate 165 0D AND ; Logical AND 166 1E SKZ ; Skip on Accumulator Zero 167 9F T 15F ; Transfer 168 05 RTN ; Return ;set FF1 if bit x of mem(@B) is not set 169 7E LDI 1 ; Load Accumulator Immediate 16A 7D LDI 2 ; Load Accumulator Immediate 16B 7B LDI 4 ; Load Accumulator Immediate 16C 77 LDI 8 ; Load Accumulator Immediate 16D 0D AND ; Logical AND 16E 1E SKZ ; Skip on Accumulator Zero 16F 05 RTN ; Return 170 9F T 15F ; Transfer ;reset FF1 if bit x of mem(@B) is set 171 7E LDI 1 ; Load Accumulator Immediate 172 7D LDI 2 ; Load Accumulator Immediate 173 7B LDI 4 ; Load Accumulator Immediate 174 77 LDI 8 ; Load Accumulator Immediate 175 16 SKF1 ; Skip if FF1 Equals 1 176 05 RTN ; Return 177 0D AND ; Logical AND 178 1E SKZ ; Skip on Accumulator Zero 179 9A T 15A ; Transfer 17A 05 RTN ; Return ;mem(@B)-- if mem(@B) is not zero 17B 70 LDI F ; Load Accumulator Immediate 17C 09 ADSK ; Add and skip on carry-out 17D 07 RTNSK ; Return and Skip ;147-> EX 0, RTN 17E 87 T 147 ; Transfer 180 00 SET NIB #0 ; Load B Long ;toggle bit x of mem(@B) only if FF1==1 180 7E LDI 1 ; Load Accumulator Immediate 181 7D LDI 2 ; Load Accumulator Immediate 182 7B LDI 4 ; Load Accumulator Immediate 183 77 LDI 8 ; Load Accumulator Immediate 184 16 SKF1 ; Skip if FF1 Equals 1 185 05 RTN ; Return 186 1B LXA ; Load X Register from Accumulator 187 0D AND ; Logical AND 188 1E SKZ ; Skip on Accumulator Zero 189 8E T 18E ; Transfer ;bit x of mem(@B) is 0 18A 1A XAX ; Exchange Accumulator and X 18B 0B AD ; Add 18C 3F EX 0 ; Exchange Accumulator and Memory 18D 05 RTN ; Return ;bit x of mem(@B) is 1 18E 0E COMP ; Complement 18F 0D AND ; Logical AND 190 8C T 18C ; Transfer ;bit test operation if bit(mem(@B))==1 RTNSK else RTN 191 7E LDI 1 ; Load Accumulator Immediate 192 7D LDI 2 ; Load Accumulator Immediate 193 7B LDI 4 ; Load Accumulator Immediate 194 77 LDI 8 ; Load Accumulator Immediate 195 0D AND ; Logical AND 196 1E SKZ ; Skip on Accumulator Zero 197 07 RTNSK ; Return and Skip 198 05 RTN ; Return ;test if mem(@B) == 0 199 37 LD 0 ; Load Accumulator from Memory 19A 1E SKZ ; Skip on Accumulator Zero 19B 05 RTN ; Return 19C 07 RTNSK ; Return and Skip ;dead code? or called by optional eprom ;depending on game inside it, but at least not the screech 19D 7E LDI 1 ; Load Accumulator Immediate 19E 0D AND ; Logical AND 19F 1E SKZ ; Skip on Accumulator Zero 1A0 A2 T 1A2 ; Transfer 1A1 05 RTN ; Return ;here Acc=0 (comes from skz above) ==> sound off 1A2 1C D6 IOL D6 ; Input/Output Long 1A4 73 LDI C ; Load Accumulator Immediate 1A5 0D AND ; Logical AND 1A6 3F EX 0 ; Exchange Accumulator and Memory 1A7 17 INCB ; Increment BL 1A8 12 LAX ; Load Accumulator from X Register 1A9 0C EOR ; Logical Exclusive-OR 1AA 1E SKZ ; Skip on Accumulator Zero 1AB 05 RTN ; Return ;end of dead code ;subroutine entry point 1 1AC 00 96 LBL 069 ; Load B Long ;subroutine entry point 2 1AE 00 97 LBL 068 ; Load B Long 1B0 7E LDI 1 ; Load Accumulator Immediate 1B1 0B AD ; Add 1B2 3F EX 0 ; Exchange Accumulator and Memory ;RF1, and goto 005 1B3 51 03 TL 103 ; Transfer Long 1B5 52 00 TL 200 ; Transfer Long 1B7 54 E2 TL 4E2 ; Transfer Long ;jump eprom. on screech 1B9 58 D0 TL 8D0 ; Transfer Long 1BB 58 E0 TL 8E0 ; Transfer Long ;1BD 00 55 LBL 0AA ; Load B Long 1BE 1BE 55 B2 TL 5B2 ;reconstituted from call existing for 5B2 ;1BF B2 T 1B2 ; Transfer ;SAG masks all bits in bu,bm. ;entry params are A,BL,X 1C0 13 SAG ; Special Address Generation 1C1 37 LD 0 ; Load Accumulator from Memory 1C2 0C EOR ; Logical Exclusive-OR 1C3 1E SKZ ; Skip on Accumulator Zero 1C4 07 RTNSK ; Return and Skip 1C5 17 INCB ; Increment BL 1C6 12 LAX ; Load Accumulator from X Register 1C7 0C EOR ; Logical Exclusive-OR 1C8 1E SKZ ; Skip on Accumulator Zero 1C9 07 RTNSK ; Return and Skip 1CA 05 RTN ; Return ;if mem(@E9)&b0001==0 RTNSK else RTN 1CB 00 16 LBL 0E9 ; Load B Long 1CD 7E LDI 1 ; Load Accumulator Immediate 1CE 0D AND ; Logical AND 1CF 1E SKZ ; Skip on Accumulator Zero 1D0 05 RTN ; Return 1D1 07 RTNSK ; Return and Skip ;X is untouched ;BL is saved in work memory @0, and restored in the end ;work mem @1 is used internally, and reset to #0 at exit ;delay for x ms. 6832cyclx5us==>34ms per call ;this routine is made of 3 intricated counters ; mem @1 counts up from 7 to 0 ; BL counts from 0 to 0 (16 steps) ; A counts from 0 to 0 (16 steps) 1D2 7F LDI 0 ; Acc<-0 1D3 19 XABL ; 1D4 13 SAG 1D5 3F EX 0 ; BL is saved in @0 1D6 17 INCB ; BL is now 1 1D7 78 LDI 7 ; 1D8 13 SAG 1D9 3F EX 0 ; @1<-7 1DA 7F LDI 0 ; 1DB 9C T 1DC ; NOP 1DC 6E ADI 1 1DD 9B T 1DB ; loop on nop for 16 times A:0..F 1DE 17 INCB ; 1DF 9A T 1DA ; loop again on 16 times BL:1..0 1E0 17 INCB ; BL<-1 here, since we skipped from 1DE 1E1 24 RC ; Reset Carry flip-flop 1E2 7E LDI 1 1E3 13 SAG 1E4 0B AD 1E5 13 SAG 1E6 3F EX 0 ; @1<-@1++ 1E7 15 SKC ; Skip on Carry flip-flop 1E8 9A T 1DA ; 3rd loop @1:7..0 ;now @1 contains #0 1E9 1F DECB ; BL back to 0, to restore initial BL value 1EA 13 SAG 1EB 3F EX 0 ; get back initial BL 1EC 19 XABL ; restore BL 1ED 05 RTN ; Return ;A is saved, and restored, using mem @[X]BL X started at 3 ;set BM=1 ;then goto 772 1EE 18 XBMX ; Exchange BM and X 1EF 3F EX 0 ; Exchange Accumulator and Memory 1F0 7F LDI 0 ; Load Accumulator Immediate ;loop 16 calls to IOL DB with Acc from 0 to F ;which means reset all outputs in group ABCD 1F1 1B LXA ; Load X Register from Accumulator 1F2 1C DB IOL DB ; Input/Output Long ;the return value of iol is not read 1F4 12 LAX ; Load Accumulator from X Register 1F5 6E ADI 1 ; Add Immediate and skip on carry-out 1F6 B1 T 1F1 ; Transfer 1F7 7E LDI 1 ; Load Accumulator Immediate Acc<-#1 1F8 1B LXA ; Load X Register from Accumulator X<-#1 1F9 37 LD 0 ; Load Accumulator from Memory Acc<-mem 1FA 18 XBMX ; Exchange BM and X 1FB 57 72 TL 772 ; Transfer Long 1FD 00 00 LBL 0FF ; Load B Long 1FF 00 SET NIB #0 ; Load B Long 200 CD LB (CD) (B<=059) 201 3F EX 0 202 7C LDI 3 203 0D AND ; Logical AND 204 6E ADI 1 ; Add Immediate and skip on carry-out 205 2F EXD 0 ; Exchange Accumulator and Memory and decrement BL 206 3F EX 0 ; Exchange Accumulator and Memory 207 73 LDI C ; Load Accumulator Immediate 208 0D AND ; Logical AND 209 68 ADI 7 ; Add Immediate and skip on carry-out 20A 6C ADI 3 ; Add Immediate and skip on carry-out 20B 8C T 20C ; Transfer 20C 68 ADI 7 ; Add Immediate and skip on carry-out 20D 66 ADI 9 ; Add Immediate and skip on carry-out 20E 8F T 20F ; Transfer 20F 3F EX 0 ; Exchange Accumulator and Memory 210 16 SKF1 ; Skip if FF1 Equals 1 211 05 RTN ; Return 212 22 SF1 ; Set FF1 213 00 A7 LBL 058 ; Load B Long 215 37 LD 0 ; Load Accumulator from Memory 216 60 ADI F ; Add Immediate and skip on carry-out 217 05 RTN ; Return 218 3F EX 0 ; Exchange Accumulator and Memory 219 17 INCB ; Increment BL 21A 37 LD 0 ; Load Accumulator from Memory 21B 1B LXA ; Load X Register from Accumulator ;jump to optional eprom, 21E for screech 21C 58 FE TL 8FE ; Transfer Long 21E C8 LB (C8) (B<=042) 21F CB LB (CB) (B<=052) 220 7D LDI 2 221 0D AND ; Logical AND 222 1E SKZ ; Skip on Accumulator Zero 223 B0 T 230 ; Transfer 224 42 SKBI 2 ; Skip if BL equals to Immediate. 225 AA T 22A ; Transfer 226 11 LABL ; Load Accumulator with BL 227 67 ADI 8 ; Add Immediate and skip on carry-out 228 19 XABL ; Exchange Accumulator and BL 229 A1 T 221 ; Transfer 22A 18 XBMX ; Exchange BM and X 22B 12 LAX ; Load Accumulator from X Register 22C 18 XBMX ; Exchange BM and X 22D 64 ADI B ; Add Immediate and skip on carry-out 22E 9F T 21F ; Transfer 22F 05 RTN ; Return 230 19 XABL ; Exchange Accumulator and BL 231 13 SAG ; Special Address Generation 232 3F EX 0 ; Exchange Accumulator and Memory 233 12 LAX ; Load Accumulator from X Register 234 13 SAG ; Special Address Generation 235 0B AD ; Add 236 19 XABL ; Exchange Accumulator and BL 237 12 LAX ; Load Accumulator from X Register 238 60 ADI F ; Add Immediate and skip on carry-out 239 BA T 23A ; Transfer 23A 52 42 TL 242 ; Transfer Long 23C 58 E0 TL 8E0 ; Transfer Long 23E 55 B0 TL 5B0 ; Transfer Long 240 12 LAX ; Load Accumulator from X Register 241 6E ADI 1 ; Add Immediate and skip on carry-out 242 1B LXA ; Load X Register from Accumulator 243 1C D6 IOL D6 ; Input/Output Long 245 D2 TM (D2) (target addr=122) ; jsr BCD mem(@B)++ 246 93 T 253 ; Transfer 247 17 INCB ; Increment BL 248 8A T 24A ; Transfer 249 8C T 24C ; Transfer 24A 48 SKBI 8 ; Skip if BL equals to Immediate. 24B 80 T 240 ; Transfer 24C 11 LABL ; Load Accumulator with BL 24D 65 DC ; Decimal Correction 24E 19 XABL ; Exchange Accumulator and BL 24F 70 LDI F ; Load Accumulator Immediate 250 1C D3 IOL D3 ; Input/Output Long ;bit 0100 set in memory at @(B reg) only if FF1 is 1 252 DA TM (DA) (target addr=142) ; Transfer and Mark Indirect 253 11 LABL ; Load Accumulator with BL 254 6D ADI 2 ; Add Immediate and skip on carry-out 255 98 T 258 ; Transfer 256 71 LDI E ; Load Accumulator Immediate 257 9E T 25E ; Transfer 258 69 ADI 6 ; Add Immediate and skip on carry-out 259 9B T 25B ; Transfer 25A A0 T 260 ; Transfer 25B 6D ADI 2 ; Add Immediate and skip on carry-out 25C A0 T 260 ; Transfer 25D 79 LDI 6 ; Load Accumulator Immediate 25E 52 A2 TL 2A2 ; Transfer Long 260 19 XABL ; Exchange Accumulator and BL 261 67 ADI 8 ; Add Immediate and skip on carry-out 262 7D LDI 2 ; Load Accumulator Immediate 263 75 LDI A ; Load Accumulator Immediate 264 19 XABL ; Exchange Accumulator and BL 265 37 LD 0 ; Load Accumulator from Memory 266 67 ADI 8 ; Add Immediate and skip on carry-out 267 AA T 26A ; Transfer 268 52 85 TL 285 ; Transfer Long 26A 6B ADI 4 ; Add Immediate and skip on carry-out 26B BA T 27A ; Transfer 26C 19 XABL ; Exchange Accumulator and BL 26D 6A ADI 5 ; Add Immediate and skip on carry-out 26E 19 XABL ; Exchange Accumulator and BL 26F 35 LD 2 ; Load Accumulator from Memory 270 0C EOR ; Logical Exclusive-OR 271 1E SKZ ; Skip on Accumulator Zero 272 BC T 27C ; Transfer 273 3F EX 0 ; Exchange Accumulator and Memory 274 2D EXD 2 ; Exchange Accumulator and Memory and decrement BL 275 42 SKBI 2 ; Skip if BL equals to Immediate. 276 B8 T 278 ; Transfer 277 BA T 27A ; Transfer 278 4A SKBI A ; Skip if BL equals to Immediate. 279 AF T 26F ; Transfer ;RF1, and goto 005 27A 51 03 TL 103 ; Transfer Long 27C 52 80 TL 280 ; Transfer Long ;subroutines that just reads data in of HM6508 27E 55 38 TL 538 ; Transfer Long ;280 from: 27C 52 80 TL 280 which is called only once from 272 280 35 LD 2 ; Load Accumulator from Memory 281 0E COMP ; Complement 282 09 ADSK ; Add and skip on carry-out 283 A0 T 2A0 ; Transfer 284 25 RF2 ; Reset FF2 285 19 XABL ; Exchange Accumulator and BL 286 67 ADI 8 ; Add Immediate and skip on carry-out 287 7D LDI 2 ; Load Accumulator Immediate 288 75 LDI A ; Load Accumulator Immediate 289 19 XABL ; Exchange Accumulator and BL 28A 1C D3 IOL D3 ; Input/Output Long ;bit b1000 set in memory at @(B reg) only if FF1 is 1 28C DB TM (DB) (target addr=143) ; set bit 1000b of current ram nibble 28D 19 XABL ; Exchange Accumulator and BL 28E 6A ADI 5 ; Add Immediate and skip on carry-out 28F 19 XABL ; Exchange Accumulator and BL 290 35 LD 2 ; Load Accumulator from Memory 291 2D EXD 2 ; Exchange Accumulator and Memory and decrement BL 292 42 SKBI 2 ; Skip if BL equals to Immediate. 293 95 T 295 ; Transfer 294 97 T 297 ; Transfer 295 4A SKBI A ; Skip if BL equals to Immediate. 296 90 T 290 ; Transfer 297 14 SKF2 ; Skip if FF2 Equals 1 298 9A T 29A ; Transfer 299 A0 T 2A0 ; Transfer 29A 21 SF2 ; Set FF2 29B 00 96 LBL 069 ; Load B Long 29D 7C LDI 3 ; Load Accumulator Immediate 29E 7E LDI 1 ; Load Accumulator Immediate 29F D1 TM (D1) (target addr=118) ; Transfer and Mark Indirect ;RF1, and goto 005 2A0 51 03 TL 103 ; Transfer Long 2A2 19 XABL ; Exchange Accumulator and BL 2A3 37 LD 0 ; Load Accumulator from Memory 2A4 1B LXA ; Load X Register from Accumulator 2A5 17 INCB ; Increment BL 2A6 37 LD 0 ; Load Accumulator from Memory 2A7 00 FF LBL 000 ; Load B Long 2A9 39 EX 6 ; Exchange Accumulator and Memory ;call 1C0 with B=060, A=mem(@0), X=? 2AA 01 C0 TML 1C0 ; Transfer and Mark Long 2AC B9 T 2B9 ; Transfer 2AD 00 8F LBL 070 ; Load B Long 2AF 01 C0 TML 1C0 ; Transfer and Mark Long 2B1 B9 T 2B9 ; Transfer 2B2 00 7F LBL 080 ; Load B Long 2B4 01 C0 TML 1C0 ; Transfer and Mark Long 2B6 BB T 2BB ; Transfer 2B7 52 DF TL 2DF ; Transfer Long 2B9 00 96 LBL 069 ; Load B Long 2BB 00 97 LBL 068 ; Load B Long 2BD 9E T 29E ; Transfer 2BE 58 C0 TL 8C0 ; Transfer Long 2C0 1A XAX ; Exchange Accumulator and X 2C1 1C 21 IOL 21 ; Input/Output Long 2C3 17 INCB ; Increment BL 2C4 8D T 2CD ; Transfer 2C5 00 EA LBL 015 ; Load B Long 2C7 36 LD 1 ; Load Accumulator from Memory 2C8 3E EX 1 ; Exchange Accumulator and Memory 2C9 0E COMP ; Complement 2CA 2F EXD 0 ; Exchange Accumulator and Memory and decrement BL 2CB 87 T 2C7 ; Transfer 2CC 53 13 TL 313 ; Transfer Long 2CE 56 93 TL 693 ; Transfer Long 2D0 C8 LB (C8) (B<=042) 2D1 C9 LB (C9) (B<=04A) 2D2 73 LDI C 2D3 0D AND ; Logical AND 2D4 3E EX 1 ; Exchange Accumulator and Memory 2D5 73 LDI C ; Load Accumulator Immediate 2D6 0D AND ; Logical AND 2D7 3F EX 0 ; Exchange Accumulator and Memory 2D8 4A SKBI A ; Skip if BL equals to Immediate. 2D9 91 T 2D1 ; Transfer 2DA 70 LDI F ; Load Accumulator Immediate 2DB 78 LDI 7 ; Load Accumulator Immediate 2DC 77 LDI 8 ; Load Accumulator Immediate 2DD 51 05 TL 105 ; Transfer Long 2DF C8 LB (C8) (B<=042) 2E0 F5 TM (F5) ;(target addr=192) 2E1 A3 T 2E3 2E2 AC T 2EC ; Transfer 2E3 C9 LB (C9) (B<=04A) 2E4 F5 TM (F5) ;(target addr=192) 2E5 A7 T 2E7 2E6 AC T 2EC 2E7 CA LB (CA) (B<=05A) 2E8 F5 TM (F5) ;(target addr=192) 2E9 AB T 2EB 2EA AC T 2EC 2EB CB LB (CB) (B<=052) 2EC 17 INCB 2ED 52 60 TL 260 2EF 77 LDI 8 2F0 1C D2 IOL D2 2F2 53 C7 TL 3C7 ;entry point for copy all RAM to HM6508 ;IO5 is counter reset. release from reset 2F4 00 FA LBL 005 ; Load B Long 2F6 7F LDI 0 ; Load Accumulator Immediate 2F7 1C 41 IOL 41 ; Input/Output Long 2F9 00 FC LBL 003 ; Load B Long 2FB 7F LDI 0 ; Load Accumulator Immediate 2FC 2F EXD 0 ; Exchange Accumulator and Memory and decrement BL 2FD 7F LDI 0 ; Load Accumulator Immediate ;goto 5C0 with A=0, BL=002, mem(@003)=0 ;2FE means that full copy RAM->NVRAM is required, and restart afterwards ;cannot be the trigger address to save internal NVRAM ;because at this time, NVRAM has not been written yet... ;the good trigger is 5FC or 3C0 (end of transfer) 2FE 55 C0 TL 5C0 ; Transfer Long 300 16 SKF1 ; Skip if FF1 Equals 1 301 97 T 317 ; Transfer 302 00 BD LBL 042 ; Load B Long 304 7E LDI 1 ; Load Accumulator Immediate 305 0D AND ; Logical AND 306 1E SKZ ; Skip on Accumulator Zero 307 8A T 30A ; Transfer 308 58 FC TL 8FC ; Transfer Long 30A C7 LB (C7) (B<=0E0) 30B F4 TM (F4) ;(target addr=191) 30C 8F T 30F 30D 58 00 TL 800 30F 58 FA TL 8FA 311 52 12 TL 212 313 14 SKF2 ; Skip if FF2 Equals 1 314 80 T 300 ; Transfer 315 16 SKF1 ; Skip if FF1 Equals 1 316 91 T 311 ; Transfer 317 00 96 LBL 069 ; Load B Long 319 D6 TM (D6) (target addr=17B) ; Transfer and Mark Indirect 31A A0 T 320 ; Transfer 31B 00 97 LBL 068 ; Load B Long 31D D6 TM (D6) (target addr=17B) ; Transfer and Mark Indirect 31E B8 T 338 ; Transfer 31F BA T 33A ; Transfer 320 00 87 LBL 078 ; Load B Long 322 F8 TM (F8) (target addr=199) ; Transfer and Mark Indirect 323 B4 T 334 ; Transfer 324 C3 LB (C3) (B<=040) 325 D2 TM (D2) ;(target addr=122) 326 AA T 32A 327 76 LDI 9 ; Load Accumulator Immediate 328 3F EX 0 ; Exchange Accumulator and Memory 329 9B T 31B ; Transfer 32A 00 54 LBL 0AB ; Load B Long 32C D4 TM (D4) (target addr=12D) ; Transfer and Mark Indirect 32D 00 4C LBL 0B3 ; Load B Long 32F D4 TM (D4) (target addr=12D) ; Transfer and Mark Indirect ;activate knocker 330 79 LDI 6 ; Load Accumulator Immediate 331 1C D6 IOL D6 ; Input/Output Long 333 9B T 31B ; Transfer 334 C5 LB (C5) (B<=0B1) 335 F6 TM (F6) ;(target addr=193) 336 9B T 31B 337 A4 T 324 338 53 40 TL 340 33A C8 LB (C8) (B<=042) 33B F4 TM (F4) ;(target addr=191) 33C BE T 33E 33D 8F T 30F 33E 54 AF TL 4AF 340 81 T 341 341 82 T 342 342 C5 LB (C5) (B<=0B1) 343 F5 TM (F5) ;(target addr=192) 344 86 T 346 345 91 T 351 346 26 RF1 347 F4 TM (F4) ;(target addr=191) 348 8D T 34D 349 C4 LB (C4) (B<=041) 34A F8 TM (F8) ;(target addr=199) 34B A3 T 363 34C 91 T 351 34D CF LB (CF) (B<=017) 34E F5 TM (F5) ;(target addr=192) 34F 91 T 351 350 A3 T 363 351 C4 LB (C4) (B<=041) 352 7F LDI 0 353 16 SKF1 354 3F EX 0 355 D2 TM (D2) ;(target addr=122) 356 9A T 35A 357 76 LDI 9 358 3F EX 0 359 A3 T 363 35A CF LB (CF) (B<=017) 35B 22 SF1 35C D9 TM (D9) ;(target addr=141) 35D 00 5C LBL 0A3 35F D4 TM (D4) ;(target addr=12D) ;activate knocker 360 79 LDI 6 361 1C D6 IOL D6 363 51 0E TL 10E ;365 00 55 LBL 0AA ; Load B Long ;subroutine reads data in of HM6508 366 55 28 TL 528 ;reconstituted manually ;367 28 EXD 7 ; Exchange Accumulator and Memory and decrement BL 368 55 80 TL 580 ; Transfer Long ;subroutine display result of selftest x 36A 57 8D TL 78D ; Transfer Long 36C 57 78 TL 778 ; Transfer Long 36E 57 EA TL 7EA ; selftest of coils 370 00 16 LBL 0E9 ; Load B Long 372 7E LDI 1 ; Load Accumulator Immediate 373 0D AND ; Logical AND 374 00 86 LBL 079 ; Load B Long 376 1E SKZ ; Skip on Accumulator Zero 377 BC T 37C ; Transfer 378 7B LDI 4 ; Load Accumulator Immediate 379 3F EX 0 ; Exchange Accumulator and Memory 37A 53 80 TL 380 ; Transfer Long 37C 0B AD ; Add 37D 3F EX 0 ; Exchange Accumulator and Memory 37E 50 0B TL 00B ; Transfer Long 380 C0 LB (C0) (B<=048) 381 F8 TM (F8) ;(target addr=199) 382 86 T 386 383 CB LB (CB) (B<=052) 384 F8 TM (F8) ;(target addr=199) 385 90 T 390 386 22 SF1 387 C2 LB (C2) (B<=051) 388 D6 TM (D6) ;(target addr=17B) 389 95 T 395 38A 1F DECB 38B D6 TM (D6) ;(target addr=17B) 38C 92 T 392 38D C3 LB (C3) (B<=040) 38E D6 TM (D6) ;(target addr=17B) 38F 96 T 396 390 51 0E TL 10E 392 17 INCB 393 76 LDI 9 394 3F EX 0 395 7F LDI 0 396 70 LDI F 397 00 87 LBL 078 399 3F EX 0 39A 00 5E LBL 0A1 39C DE TM (DE) ;(target addr=14B) 39D C0 LB (C0) (B<=048) 39E F8 TM (F8) ;(target addr=199) 39F AD T 3AD 3A0 C9 LB (C9) (B<=04A) 3A1 E4 TM (E4) ;(target addr=151) 3A2 16 SKF1 3A3 A9 T 3A9 3A4 CA LB (CA) (B<=05A) 3A5 E4 TM (E4) ;(target addr=151) 3A6 16 SKF1 3A7 A9 T 3A9 3A8 CB LB (CB) (B<=052) 3A9 22 SF1 3AA D8 TM (D8) ;(target addr=140) 3AB 54 80 TL 480 3AD CF LB (CF) (B<=017) 3AE 7F LDI 0 3AF 2F EXD 0 3B0 AE T 3AE 3B1 00 B0 LBL 04F 3B3 42 SKBI 2 3B4 7F LDI 0 3B5 7C LDI 3 3B6 3E EX 1 3B7 7F LDI 0 3B8 2E EXD 1 3B9 41 SKBI 1 3BA B3 T 3B3 3BB 7F LDI 0 3BC 3A EX 5 3BD 79 LDI 6 3BE 54 7C TL 47C ; probably general entry point (here just after copy RAM->NVRAM) 3C0 22 SF1 3C1 C0 LB (C0) (B<=048) 3C2 F7 TM (F7) ;(target addr=194) test bit 1000 3C3 B1 T 3F1 3C4 DF TM (DF) ;(target addr=14C) 3C5 52 EF TL 2EF 3C7 C4 LB (C4) (B<=041) 3C8 D6 TM (D6) ;(target addr=17B) 3C9 B5 T 3F5 3CA C8 LB (C8) (B<=042) 3CB F5 TM (F5) ;(target addr=192) 3CC 90 T 3D0 3CD DD TM (DD) ;(target addr=14A) 3CE C9 LB (C9) (B<=04A) 3CF 9B T 3DB 3D0 C9 LB (C9) (B<=04A) 3D1 F5 TM (F5) ;(target addr=192) 3D2 96 T 3D6 3D3 DD TM (DD) ;(target addr=14A) 3D4 CA LB (CA) (B<=05A) 3D5 9B T 3DB 3D6 CA LB (CA) (B<=05A) 3D7 F5 TM (F5) ;(target addr=192) 3D8 9E T 3DE 3D9 DD TM (DD) ;(target addr=14A) 3DA CB LB (CB) (B<=052) 3DB F4 TM (F4) ;(target addr=191) 3DC A0 T 3E0 3DD B6 T 3F6 3DE CB LB (CB) (B<=052) 3DF DD TM (DD) ;(target addr=14A) 3E0 C8 LB (C8) (B<=042) 3E1 D9 TM (D9) ;(target addr=141) 3E2 C0 LB (C0) (B<=048) 3E3 D0 TM (D0) ;(target addr=117) 3E4 C5 LB (C5) (B<=0B1) 3E5 E7 TM (E7) ;(target addr=154) 3E6 C0 LB (C0) (B<=048) 3E7 16 SKF1 3E8 74 LDI B 3E9 72 LDI D 3EA 09 ADSK 3EB B7 T 3F7 3EC 7A LDI 5 3ED 3F EX 0 3EE 25 RF2 ;RF1, and goto 005 3EF 51 03 TL 103 ; Transfer Long 3F1 CD LB (CD) (B<=059) 3F2 F8 TM (F8) ;(target addr=199) 3F3 85 T 3C5 3F4 B7 T 3F7 3F5 CF LB (CF) (B<=017) 3F6 D9 TM (D9) ;(target addr=141) 3F7 CD LB (CD) (B<=059) 3F8 7F LDI 0 3F9 3F EX 0 ; Exchange Accumulator and Memory ;activate ball home 3FA 78 LDI 7 ; Load Accumulator Immediate 3FB 1C D6 IOL D6 ; Input/Output Long 3FD 21 SF2 ; Set FF2 3FE 54 80 TL 480 ; Transfer Long 400 54 4C TL 44C ; Transfer Long ;bit 0100 set in memory at @(B reg) only if FF1 is 1 402 DA TM (DA) (target addr=142) ; Transfer and Mark Indirect 403 12 LAX ; Load Accumulator from X Register 404 B4 T 434 ; Transfer 405 01 CB TML 1CB ; Transfer and Mark Long 407 8B T 40B ; Transfer 408 00 7C LBL 083 ; Load B Long 40A D4 TM (D4) (target addr=12D) ; Transfer and Mark Indirect 40B 00 5F LBL 0A0 ; Load B Long 40D 22 SF1 ; Set FF1 40E E3 TM (E3) (target addr=183) ; Transfer and Mark Indirect 40F E6 TM (E6) (target addr=153) ; Transfer and Mark Indirect 410 EB TM (EB) (target addr=164) ; Transfer and Mark Indirect 411 16 SKF1 ; Skip if FF1 Equals 1 412 80 T 400 ; Transfer 413 A6 T 426 ; Transfer 414 01 CB TML 1CB ; Transfer and Mark Long 416 9A T 41A ; Transfer 417 00 64 LBL 09B ; Load B Long 419 D4 TM (D4) (target addr=12D) ; Transfer and Mark Indirect 41A 00 4F LBL 0B0 ; Load B Long 41C 37 LD 0 ; Load Accumulator from Memory 41D A9 T 429 ; Transfer 41E 01 CB TML 1CB ; Transfer and Mark Long 420 A4 T 424 ; Transfer 421 00 74 LBL 08B ; Load B Long 423 D4 TM (D4) (target addr=12D) ; Transfer and Mark Indirect 424 00 5E LBL 0A1 ; Load B Long 426 7C LDI 3 ; Load Accumulator Immediate 427 0D AND ; Logical AND 428 6E ADI 1 ; skip with 2-cycl below 429 00 5E LBL 0A1 ; Load B Long 42B 22 SF1 ; Set FF1 42C 1B LXA ; Load X Register from Accumulator 42D 73 LDI C ; Load Accumulator Immediate 42E 0D AND ; Logical AND 42F 6B ADI 4 ; Add Immediate and skip on carry-out 430 82 T 402 ; Transfer 431 DE TM (DE) (target addr=14B) ; Transfer and Mark Indirect 432 12 LAX ; Load Accumulator from X Register 433 6E ADI 1 ; Add Immediate and skip on carry-out 434 1B LXA ; Load X Register from Accumulator 435 00 16 LBL 0E9 ; Load B Long 437 F4 TM (F4) (target addr=191) ; Transfer and Mark Indirect 438 BD T 43D ; Transfer 439 00 44 LBL 0BB ; Load B Long 43B 12 LAX ; Load Accumulator from X Register 43C D5 TM (D5) (target addr=12E) ; Transfer and Mark Indirect 43D 12 LAX ; Load Accumulator from X Register 43E 54 40 TL 440 ; Transfer Long 440 00 4C LBL 0B3 ; Load B Long 442 D5 TM (D5) (target addr=12E) ; Transfer and Mark Indirect 443 C2 LB (C2) (B<=051) 444 D3 TM (D3) ;(target addr=123) 445 8D T 44D 446 1F DECB 447 30 LD 7 ; Load Accumulator from Memory 448 0E COMP ; Complement 449 09 ADSK ; Add and skip on carry-out 44A 90 T 450 ; Transfer 44B 30 LD 7 ; Load Accumulator from Memory 44C D0 TM (D0) (target addr=117) ; Transfer and Mark Indirect 44D 22 SF1 ; Set FF1 44E 50 0B TL 00B ; Transfer Long 450 30 LD 7 ; Load Accumulator from Memory 451 3F EX 0 ; Exchange Accumulator and Memory 452 17 INCB ; Increment BL 453 76 LDI 9 ; Load Accumulator Immediate 454 3F EX 0 ; Exchange Accumulator and Memory 455 8D T 44D ; Transfer 456 14 SKF2 ; Skip if FF2 Equals 1 457 58 00 TL 800 ; Transfer Long 459 A6 T 466 ; Transfer 45A F8 TM (F8) (target addr=199) ; Transfer and Mark Indirect 45B 9E T 45E ; Transfer 45C 53 F7 TL 3F7 ; Transfer Long 45E 54 D3 TL 4D3 ; Transfer Long 460 9C T 45C ; Transfer 461 00 86 LBL 079 ; Load B Long ;461 463 37 LD 0 ; Load Accumulator from Memory 464 6B ADI 4 ; Add Immediate and skip on carry-out 465 A8 T 468 ; Transfer 466 51 0E TL 10E ; Transfer Long 468 69 ADI 6 ; Add Immediate and skip on carry-out 469 A6 T 466 ; Transfer 46A 7E LDI 1 ; Load Accumulator Immediate 46B 0C EOR ; Logical Exclusive-OR 46C 1B LXA ; Load X Register from Accumulator 46D C1 LB (C1) (B<=0E9) 46E 73 LDI C 46F 0D AND 470 1E SKZ 471 B3 T 473 ; Transfer 472 A6 T 466 ; Transfer 473 67 ADI 8 ; Add Immediate and skip on carry-out 474 7F LDI 0 ; Load Accumulator Immediate 475 7E LDI 1 ; Load Accumulator Immediate 476 19 XABL ; Exchange Accumulator and BL 477 18 XBMX ; Exchange BM and X 478 7E LDI 1 ; Load Accumulator Immediate 479 0B AD ; Add 47A 3F EX 0 ; Exchange Accumulator and Memory 47B A6 T 466 ; Transfer 47C 1C D3 IOL D3 ; Input/Output Long 47E 58 00 TL 800 ; Transfer Long 480 7E LDI 1 ; Load Accumulator Immediate 481 1C D3 IOL D3 ; Input/Output Long 483 01 D2 TML 1D2 ; Transfer and Mark Long 485 51 11 TL 111 ; Transfer Long 487 00 47 LBL 0B8 ; Load B Long 489 F8 TM (F8) (target addr=199) ; Transfer and Mark Indirect 48A 9F T 49F ; Transfer 48B D2 TM (D2) (target addr=122) ; jsr BCD mem(@B)++ 48C 17 INCB ; Increment BL 48D 75 LDI A ; Load Accumulator Immediate 48E 3F EX 0 ; Exchange Accumulator and Memory 48F CC LB (CC) (B<=0B9) 490 35 LD 2 491 3C EX 3 492 7F LDI 0 493 3F EX 0 ; Exchange Accumulator and Memory 494 00 B6 LBL 049 ; Load B Long 496 7E LDI 1 ; Load Accumulator Immediate 497 0D AND ; Logical AND 498 1E SKZ ; Skip on Accumulator Zero ;ldi 2=>tone /B, ldi 4=>tone /D 499 7D LDI 2 ; Load Accumulator Immediate 49A 7B LDI 4 ; Load Accumulator Immediate 49B 1C D6 IOL D6 ; Input/Output Long 49D 50 A7 TL 0A7 ; Transfer Long 49F D2 TM (D2) (target addr=122) ; jsr BCD mem(@B)++ 4A0 A4 T 4A4 ; Transfer 4A1 D2 TM (D2) (target addr=122) ; Transfer and Mark Indirect 4A2 CC LB (CC) (B<=0B9) 4A3 A9 T 4A9 4A4 D2 TM (D2) ;(target addr=122) 4A5 8F T 48F 4A6 00 00 LBL 0FF 4A8 00 D6 LBL 029 4AA F7 TM (F7) ;(target addr=194) 4AB D6 TM (D6) ;(target addr=17B) 4AC 8F T 48F 4AD 1F DECB 4AE D6 TM (D6) ;(target addr=17B) 4AF 00 B6 LBL 049 4B1 37 LD 0 4B2 1B LXA 4B3 C8 LB (C8) (B<=042) 4B4 FC TM (FC) ;(target addr=19D) 4B5 C9 LB (C9) (B<=04A) 4B6 FC TM (FC) ;(target addr=19D) 4B7 CA LB (CA) (B<=05A) 4B8 FC TM (FC) ;(target addr=19D) 4B9 CB LB (CB) (B<=052) 4BA FC TM (FC) ;(target addr=19D) 4BB 22 SF1 4BC 50 0B TL 00B 4BE 00 00 LBL 0FF ;(de)activate coil #8..F, resp. to ldi, before resetting reset 4C0 77 LDI 8 4C1 76 LDI 9 ; Load Accumulator Immediate 4C2 75 LDI A ; Load Accumulator Immediate 4C3 74 LDI B ; Load Accumulator Immediate 4C4 73 LDI C ; Load Accumulator Immediate 4C5 72 LDI D ; Load Accumulator Immediate 4C6 71 LDI E ; Load Accumulator Immediate 4C7 70 LDI F ; Load Accumulator Immediate 4C8 1C D6 IOL D6 ; Input/Output Long 4CA 16 SKF1 ; Skip if FF1 Equals 1 4CB 91 T 4D1 ; Transfer 4CC 14 SKF2 ; Skip if FF2 Equals 1 4CD 7D LDI 2 ; Load Accumulator Immediate 4CE 7E LDI 1 ; Load Accumulator Immediate 4CF 21 SF2 ; Set FF2 4D0 F9 TM (F9) (target addr=1B5) ; Transfer and Mark Indirect 4D1 50 05 TL 005 ; Transfer Long 4D3 CE LB (CE) (B<=016) 4D4 D6 TM (D6) ;(target addr=17B) 4D5 98 T 4D8 4D6 58 00 TL 800 4D8 CF LB (CF) (B<=017) 4D9 F6 TM (F6) ;(target addr=193) 4DA 7C LDI 3 4DB 74 LDI B 4DC F9 TM (F9) ;(target addr=1B5) 4DD B0 T 4F0 4DE 03 93 TML 393 4E0 00 00 LBL 0FF 4E2 C5 LB (C5) (B<=0B1) 4E3 F7 TM (F7) ;(target addr=194) 4E4 A9 T 4E9 4E5 CE LB (CE) (B<=016) 4E6 D0 TM (D0) ;(target addr=117) 4E7 05 RTN 4E8 05 RTN 4E9 CE LB (CE) (B<=016) 4EA D2 TM (D2) ;(target addr=122) 4EB 05 RTN 4EC 3F EX 0 4ED 05 RTN 4EE 00 00 LBL 0FF 4F0 00 96 LBL 069 4F2 F8 TM (F8) ;(target addr=199) 4F3 BA T 4FA 4F4 1F DECB 4F5 F8 TM (F8) ;(target addr=199) 4F6 BA T 4FA ;RF1, and jsr 005 4F7 01 03 TML 103 ; Transfer and Mark Long 4F9 93 T 4D3 ; Transfer 4FA C7 LB (C7) (B<=0E0) 4FB DC TM (DC) ;(target addr=149) 4FC 53 17 TL 317 4FE 00 00 LBL 0FF ; Load B Long 500 54 1E TL 41E ; Transfer Long 502 54 05 TL 405 ; Transfer Long 504 54 14 TL 414 ; Transfer Long 506 52 D0 TL 2D0 ; Transfer Long 508 54 61 TL 461 ; Transfer Long 50A 54 61 TL 461 ; Transfer Long 50C 53 70 TL 370 ; Transfer Long 50E 52 DC TL 2DC ; Transfer Long ;beginning of ram cmos test (+write to ram) ;IO5 at 1=>pin HI-Z => 0V (pull down) => NAND => 4040 reset pin at high ;IO5 at 0=>Out pin at +5V => +5V => NAND => 4040 reset pin at low => counter free ;IO5 is counter reset. release reset (of counter) ;work register @28/29<-00 510 00 FA LBL 005 ; Load B Long 512 7F LDI 0 ; Load Accumulator Immediate 513 1C 41 IOL 41 ; Input/Output Long 515 00 D6 LBL 029 ; Load B Long 517 7F LDI 0 ; Load Accumulator Immediate 518 2F EXD 0 ; Exchange Accumulator and Memory and decrement BL 519 7F LDI 0 ; Load Accumulator Immediate 51A 3F EX 0 ; Exchange Accumulator and Memory 51B 55 40 TL 540 ; Transfer Long 51D 19 XABL ; Exchange Accumulator and BL 51E 17 INCB ; Increment BL 51F 37 LD 0 ; Load Accumulator from Memory 520 69 ADI 6 ; Add Immediate and skip on carry-out 521 6D ADI 2 ; Add Immediate and skip on carry-out 522 A5 T 525 ; Transfer 523 55 6C TL 56C ; Transfer Long 525 7D LDI 2 ; Load Accumulator Immediate 526 55 64 TL 564 ; Transfer Long ;goto here from 366 ;subroutine that enables the HM6508 nvram and reads current bit data in out of HM6508 ;RTN if TTL 1, RTNSK if TTL 0 with A=0 if 0, A=1xxx if 1 ;set BL to #0 ; ;IO2 is enable HM6508 ;IO2=0 => Out +5V => HM6508 enabled, bc enable pin HM6508=0 (thru nand) 528 00 FD LBL 002 ; Load B Long 52A 7F LDI 0 ; Load Accumulator Immediate 52B 1C 41 IOL 41 ; Input/Output Long ;IO6 is STPR (bloody printer) ;=>pulse on pin1 of MD 52D 00 F9 LBL 006 ; Load B Long 52F 7F LDI 0 ; Load Accumulator Immediate 530 1C 41 IOL 41 ; Input/Output Long 532 1C 41 IOL 41 ; Input/Output Long ;IO7 is RDPR (bloody printer) ;=>RDPR becomes +5V 534 17 INCB ; Increment BL 535 7F LDI 0 ; Load Accumulator Immediate 536 1C 41 IOL 41 ; Input/Output Long ;IO0 is data in from T2. ;T2 is blocked if outHM=1, T2 is on if outHM=0 ;T2 blocked=>in=-12V (thru pull-down)=>A17 reads 1 if TTL 1 in C2 (RTN) ;T2 on =>in= +5V =>A17 reads 0 if TTL 0 in C2 (RTNSK) ; 538 00 FF LBL 000 ; Load B Long 53A 77 LDI 8 ; Load Accumulator Immediate ;next IOL will return the state of data in A 53B 1C 41 IOL 41 ; Input/Output Long 53D 1E SKZ ; Skip on Accumulator Zero 53E 05 RTN ; Return if data in is 1 53F 07 RTNSK ; Return and Skip if data in is 0 ; 540 test HM6508 and write its contents to ram ; rem: TML 366 (actually TL 528) reads bit at current CD4040 address from nvram, RTN or RTNSK if 0 or 1 (no address clock advance) ; rem: TML 368 (actually TL 580) reads HM6508 bit,then test to 1, then to 0, then repost initial value, and advance clock 4040 ; also create 1/4 of the current nibble ; will print 5xx to signal an address r/w error at xx ; init of the next nibble=>0 into @0 540 00 FF LBL 000 ; Load B Long 542 7F LDI 0 ; Load Accumulator Immediate 543 3F EX 0 ; Exchange Accumulator and Memory ;366 points to 528: subroutine starts HM6508+printer, gets data in of HM6508 544 03 66 TML 366 ; Transfer and Mark Long 546 7E LDI 1 ; Load Accumulator Immediate ;368 points to 580: 547 03 68 TML 368 ; Transfer and Mark Long 549 03 66 TML 366 ; Transfer and Mark Long 54B 7D LDI 2 ; Load Accumulator Immediate 54C 03 68 TML 368 ; Transfer and Mark Long 54E 03 66 TML 366 ; Transfer and Mark Long 550 7B LDI 4 ; Load Accumulator Immediate 551 03 68 TML 368 ; Transfer and Mark Long 553 03 66 TML 366 ; Transfer and Mark Long 555 77 LDI 8 ; Load Accumulator Immediate 556 03 68 TML 368 ; actually call is for the first bit of next nibble 558 00 D6 LBL 029 ; Load B Long 55A 35 LD 2 ; A<- (@29), B<-009 55B 2D EXD 2 ; (@9)<-(@29) B<-028, (skip if BL=0) 55C 35 LD 2 ; A<- (@28), B<-008 55D 19 XABL ; A<->BL 55E 42 SKBI 2 ; Skip if BL equals 2 (BL is currently (@28)). 55F A2 T 562 ; Transfer 562, (@28)!=2 560 55 1D TL 51D ; Transfer Long ;there is an error detected, or all is ok andwe have finished will display error code or 500 562 19 XABL ; A<->BL: BL is 008 again (vft), A is (@28) again 563 17 INCB ; BL++ 564 18 XBMX ; Exchange BM and X (to save X I think) 565 1B LXA ; X<-(@28) 566 18 XBMX ; BM<-(@28), X restored from 564 567 13 SAG ; just to use working addresses in 0..F without having to zeroing BU,BM 568 37 LD 0 ; A<-(@(0 0 BL)) 569 19 XABL ; A<->BL 56A 12 LAX ; A<-X 56B 3F EX 0 ; Exchange Accumulator and Memory 56C 00 D6 LBL 029 ; Load B Long 56E 24 RC ; Reset Carry flip-flop 56F 7E LDI 1 ; Load Accumulator Immediate 570 0B AD ; Add 571 2F EXD 0 ; Exchange Accumulator and Memory and decrement BL 572 15 SKC ; Skip on Carry flip-flop 573 80 T 540 ; Transfer handle next nibble 574 47 SKBI 7 ; @(28, 29) has rolled over, finished. If there was an error inside HM6508, display 5xx 575 AE T 56E ; Transfer ;IO5 is counter reset. reset counter 576 00 FA LBL 005 ; Load B Long 578 77 LDI 8 ; Load Accumulator Immediate 579 1C 41 IOL 41 ; Input/Output Long 57B 19 XABL ; Exchange Accumulator and BL ;36A display seltest (error in BM): A=5, BL=ret of IOL 41 57C 03 6A TML 36A ; Transfer and Mark Long 57E 52 D0 TL 2D0 ; Transfer Long ;from jsr 368 ;does 2 things: 1) continue the building of the nibble, provided that it is called 4 times ; 1') do something on the "printer" ; 2) save curr bit value, then test write 1, then 0, then restore saved value ; end) return with FF2=0 if no fault, and nibble in curr working @ which is 0, I think(?) ;is called with BL=0, and A=1|2|4|8 to build a nibble, with 4 successive calls. ;stored in a working memory, I presume 0(?) 580 0F OR ; Logical OR 581 1B LXA ; Load X Register from Accumulator 582 3F EX 0 ; accumulate flags 1 2 4 8... ;IO7 is RDPR (bloody printer) 583 00 F8 LBL 007 ; Load B Long 585 77 LDI 8 ; Load Accumulator Immediate 586 1C 41 IOL 41 ; Input/Output Long ;reads data in and RC or SC depending on its value 588 24 RC ; Reset Carry flip-flop ;27E points to 538 and is a read bit at current address of HM6805 ;RTNSK if read 0 or RTN if read 1 589 02 7E TML 27E ; Transfer and Mark Long 58B 20 SC ; last read was a 1 ;here we have RC if last read 0, or SC if last read 1 (0 or 1 is both TTL and IOL - gives same result) ;13E points to 5B1, which sets IO01 to 1, which means TTL0 into HM6805 58C 01 3E TML 13E ; Transfer and Mark Long ==>write TTL 0 into C2 58E 02 7E TML 27E ; Transfer and Mark Long ==>RTNSK if read 0 ~ TTL 0 read (which should be) 590 96 T 596 ; call here if we read 0 although we just wrote 1 ;1BE points to 5B2, which sets IO01 to 0, which means TTL1 into HM6805 591 01 BE TML 1BE ; Transfer and Mark Long 593 02 7E TML 27E ; Transfer and Mark Long==>RTNSK if read 0 ~ TTL 0 read (which shouldn't be) 595 97 T 597 ; Transfer 597 if wrote 0, read 0 596 21 SF2 ; Set FF2 to indicate a r/w problem ;23E points to 5B0, , which sets bit to 0 or 1 into HM6805 depending ;acts as 5B2 if carry is set ;acts as 5B1 if carry is not set ;here to continue hm6508 health check. FF2 is 0 if ok so far ;we now reinject the value that was initially there (marked by C, at 589) 597 02 3E TML 23E ; Transfer and Mark Long ;IO2 is enable HM6508 ;disable HM6508 599 00 FD LBL 002 ; Load B Long 59B 77 LDI 8 ; Load Accumulator Immediate 59C 1C 41 IOL 41 ; Input/Output Long ;IO4 is clk of address ;advance clock 59E 00 FB LBL 004 ; Load B Long 5A0 7F LDI 0 ; Load Accumulator Immediate 5A1 1C 41 IOL 41 ; Input/Output Long 5A3 1C 41 IOL 41 ; Input/Output Long 5A5 14 SKF2 ; Skip if FF2 Equals 1, meaning problem... 5A6 05 RTN ; Return from 368, ;the mem check at current address failed 5A7 00 D6 LBL 029 ; Load B Long 5A9 2F EXD 0 ; Exchange Accumulator and Memory and decrement BL 5AA 1A XAX ; Exchange Accumulator and X 5AB 3F EX 0 ; Exchange Accumulator and Memory 5AC 1A XAX ; Exchange Accumulator and X 5AD 18 XBMX ; Exchange BM and X 5AE 55 7B TL 57B ; Transfer Long display test result ; with error (mem loc in BM) ;subroutine 5B0 write bit to HM6805 value depends on carry ;subroutine 5B1 write bit to HM6805 value 1 ;subroutine 5B2 write bit to HM6805 value 0 ;IO(1) set bit or reset bit (5B2->reset, 5B1->set) ;IO(3) reset for 10us, then reset to previous value ; write bit at current address to HM6508 5B0 15 SKC ; Skip on Carry flip-flop 5B1 77 LDI 8 ; Load Accumulator Immediate 5B2 7F LDI 0 ; Load Accumulator Immediate ;IO1 is data out pps4->nvram 5B3 00 FE LBL 001 ; Load B Long 5B5 1C 41 IOL 41 ; Input/Output Long ;IO3 is read/write 5B7 00 FC LBL 003 ; Load B Long 5B9 7F LDI 0 ; Load Accumulator Immediate 5BA 1C 41 IOL 41 ; Input/Output Long 5BC 1C 41 IOL 41 ; Input/Output Long 5BE 05 RTN ; Return 5BF 00 SET NIB #0 ; Load B Long ;make a full copy of ram to HM6508, and restart, waiting for replay button ;goto here from 2FE with A=0, BL=002, mem(@003)=0 ;A<=mem(@002), mem(@002)<=A 5C0 3F EX 0 ; Exchange Accumulator and Memory 5C1 00 FB LBL 004 ; Load B Long 5C3 7E LDI 1 ; Load Accumulator Immediate ;mem(@004)++ starting from 1, BL<=3 5C4 2F EXD 0 ; Exchange Accumulator and Memory and decrement BL ;A<=mem(@003) 5C5 37 LD 0 ; Load Accumulator from Memory 5C6 1B LXA ; Load X Register from Accumulator ;BL<=2 5C7 1F DECB ; Decrement BL ;A<=mem(@002) 5C8 37 LD 0 ; Load Accumulator from Memory 5C9 1A XAX ; Exchange Accumulator and X 5CA 18 XBMX ; Exchange BM and X 5CB 19 XABL ; Exchange Accumulator and BL ;A<=mem((@2@3)) ;first time: send bit 0 of @2@3=00 to hm6508 5CC 37 LD 0 ; Load Accumulator from Memory 5CD 00 FB LBL 004 ; Load B Long 5CF 0D AND ; Logical AND 5D0 1E SKZ ; Skip on Accumulator Zero 5D1 7F LDI 0 ; Load Accumulator Immediate 5D2 77 LDI 8 ; Load Accumulator Immediate ;IO1 is data out to HM6508 5D3 00 FE LBL 001 ; Load B Long 5D5 1C 41 IOL 41 ; Input/Output Long ;IO2 is enable HM6508 5D7 17 INCB ; Increment BL 5D8 7F LDI 0 ; Load Accumulator Immediate 5D9 1C 41 IOL 41 ; Input/Output Long ;IO3 is read/write 5DB 17 INCB ; Increment BL 5DC 7F LDI 0 ; Load Accumulator Immediate 5DD 1C 41 IOL 41 ; Input/Output Long 5DF 1C 41 IOL 41 ; Input/Output Long ;IO2 is enable HM6508 5E1 1F DECB ; Decrement BL 5E2 77 LDI 8 ; Load Accumulator Immediate 5E3 1C 41 IOL 41 ; Input/Output Long 5E5 00 FB LBL 004 ; Load B Long ;IO4 is clk of address ;Increment HM6508 address 5E7 7F LDI 0 ; Load Accumulator Immediate 5E8 1C 41 IOL 41 ; Input/Output Long 5EA 1C 41 IOL 41 ; Input/Output Long ;A<=mem(@004)x2 5EC 37 LD 0 ; Load Accumulator from Memory 5ED 09 ADSK ; Add and skip on carry-out 5EE 84 T 5C4 ; Transfer loop to next bit to be written ;4 bits were written ;now will write next nibble if mem(@003)++ < F 5EF 2F EXD 0 ; Exchange Accumulator and Memory and decrement BL 5F0 7E LDI 1 ; Load Accumulator Immediate 5F1 09 ADSK ; Add and skip on carry-out 5F2 80 T 5C0 ; Transfer loop to next nibble to be written 5F3 2F EXD 0 ; Exchange Accumulator and Memory and decrement BL 5F4 7E LDI 1 ; Load Accumulator Immediate 5F5 09 ADSK ; Add and skip on carry-out 5F6 80 T 5C0 ; Transfer loop to next nibble to be written ;IO5 is counter reset: reset counter 5F7 00 FA LBL 005 ; Load B Long 5F9 77 LDI 8 ; Load Accumulator Immediate 5FA 1C 41 IOL 41 ; Input/Output Long 5FC 53 C0 TL 3C0 ; Transfer Long ;all RAM copied to HM6508 5FE 00 00 LBL 0FF ; Load B Long 600 16 SKF1 ; Skip if FF1 Equals 1 601 9C T 61C ; Transfer 602 00 B7 LBL 048 ; Load B Long 604 77 LDI 8 ; Load Accumulator Immediate 605 0F OR ; Logical OR 606 6B ADI 4 ; Add Immediate and skip on carry-out 607 9C T 61C ; Transfer 608 00 46 LBL 0B9 ; Load B Long 60A 77 LDI 8 ; Load Accumulator Immediate 60B 0F OR ; Logical OR 60C 6D ADI 2 ; Add Immediate and skip on carry-out 60D 9C T 61C ; Transfer 60E 9B T 61B ; Transfer 60F 00 86 LBL 079 ; Load B Long 611 37 LD 0 ; Load Accumulator from Memory 612 1B LXA ; Load X Register from Accumulator 613 A4 T 624 ; Transfer 614 14 SKF2 ; Skip if FF2 Equals 1 615 80 T 600 ; Transfer 616 00 16 LBL 0E9 ; Load B Long 618 7D LDI 2 ; Load Accumulator Immediate 619 0D AND ; Logical AND 61A 1E SKZ ; Skip on Accumulator Zero 61B 79 LDI 6 ; Load Accumulator Immediate 61C 7B LDI 4 ; Load Accumulator Immediate 61D 1B LXA ; Load X Register from Accumulator 61E 00 16 LBL 0E9 ; Load B Long 620 7E LDI 1 ; Load Accumulator Immediate 621 0D AND ; Logical AND 622 1E SKZ ; Skip on Accumulator Zero 623 8F T 60F ; Transfer 624 10 LBMX ; Load BM with X 625 70 LDI F ; Load Accumulator Immediate 626 19 XABL ; Exchange Accumulator and BL 627 1C FB IOL FB ; Input/Output Long 629 1C F7 IOL F7 ; Input/Output Long 62B 36 LD 1 ; Load Accumulator from Memory 62C 1C FE IOL FE ; Input/Output Long 62E 36 LD 1 ; Load Accumulator from Memory 62F 1C FD IOL FD ; Input/Output Long 631 1F DECB ; Decrement BL 632 B5 T 635 ; Transfer 633 56 55 TL 655 ; Transfer Long 635 12 LAX ; Load Accumulator from X Register 636 67 ADI 8 ; Add Immediate and skip on carry-out 637 6B ADI 4 ; Add Immediate and skip on carry-out 638 AB T 62B ; Transfer 639 4A SKBI A ; Skip if BL equals to Immediate. 63A BD T 63D ; Transfer 63B 56 42 TL 642 ; Transfer Long 63D 42 SKBI 2 ; Skip if BL equals to Immediate. 63E AB T 62B ; Transfer 63F BB T 63B ; Transfer 640 56 2B TL 62B ; Transfer Long 642 7B LDI 4 ; Load Accumulator Immediate 643 13 SAG ; Special Address Generation 644 0B AD ; Add 645 13 SAG ; Special Address Generation 646 3F EX 0 ; Exchange Accumulator and Memory 647 67 ADI 8 ; Add Immediate and skip on carry-out 648 80 T 640 ; Transfer 649 7A LDI 5 ; Load Accumulator Immediate 64A 0D AND ; Logical AND 64B 1C FE IOL FE ; Input/Output Long 64D 36 LD 1 ; Load Accumulator from Memory 64E 7A LDI 5 ; Load Accumulator Immediate 64F 0D AND ; Logical AND 650 1C FD IOL FD ; Input/Output Long 652 36 LD 1 ; Load Accumulator from Memory 653 56 31 TL 631 ; Transfer Long 655 1C F3 IOL F3 ; Input/Output Long 657 00 56 LBL 0A9 ; Load B Long 659 37 LD 0 ; Load Accumulator from Memory 65A 1E SKZ ; Skip on Accumulator Zero 65B AE T 66E ; Transfer 65C 75 LDI A ; Load Accumulator Immediate 65D 3F EX 0 ; Exchange Accumulator and Memory 65E 14 SKF2 ; Skip if FF2 Equals 1 65F 16 SKF1 ; Skip if FF1 Equals 1 660 A3 T 663 ; Transfer 661 00 CF LBL 030 ; Load B Long 663 00 C7 LBL 038 ; Load B Long 665 24 RC ; Reset Carry flip-flop 666 78 LDI 7 ; Load Accumulator Immediate 667 09 ADSK ; Add and skip on carry-out 668 65 DC ; Decimal Correction 669 3F EX 0 ; Exchange Accumulator and Memory 66A 15 SKC ; Skip on Carry flip-flop 66B AE T 66E ; Transfer 66C 17 INCB ; Increment BL 66D B0 T 670 ; Transfer 66E 50 0B TL 00B ; Transfer Long 670 48 SKBI 8 ; Skip if BL equals to Immediate. 671 A5 T 665 ; Transfer 672 AE T 66E ; Transfer 673 37 LD 0 ; Load Accumulator from Memory 674 56 82 TL 682 ; Transfer Long 676 00 56 LBL 0A9 ; Load B Long 678 7E LDI 1 ; Load Accumulator Immediate 679 0D AND ; Logical AND 67A 00 E8 LBL 017 ; Load B Long 67C 1E SKZ ; Skip on Accumulator Zero 67D B3 T 673 ; Transfer 67E 56 80 TL 680 ; Transfer Long 680 77 LDI 8 ; Load Accumulator Immediate 681 0D AND ; Logical AND ;something with play signal (IO24) 682 1C D5 IOL D5 ; Input/Output Long 684 1F DECB ; Decrement BL 685 37 LD 0 ; Load Accumulator from Memory 686 1C D4 IOL D4 ; Input/Output Long 688 1F DECB ; Decrement BL 689 36 LD 1 ; Load Accumulator from Memory 68A 0E COMP ; Complement 68B 3E EX 1 ; Exchange Accumulator and Memory 68C 2F EXD 0 ; Exchange Accumulator and Memory and decrement BL 68D 89 T 689 ; Transfer 68E 00 FA LBL 005 ; Load B Long 690 7F LDI 0 ; Load Accumulator Immediate 691 1B LXA ; Load X Register from Accumulator 692 97 T 697 ; Transfer 693 19 XABL ; Exchange Accumulator and BL 694 1A XAX ; Exchange Accumulator and X 695 19 XABL ; Exchange Accumulator and BL 696 1F DECB ; Decrement BL 697 7E LDI 1 ; Load Accumulator Immediate 698 0D AND ; Logical AND 699 1A XAX ; Exchange Accumulator and X 69A 19 XABL ; Exchange Accumulator and BL 69B 1A XAX ; Exchange Accumulator and X 69C 68 ADI 7 ; skip on 2-cycl below 69D 1C 21 IOL 21 ; Input/Output Long 69F 17 INCB ; Increment BL 6A0 19 XABL ; Exchange Accumulator and BL 6A1 1A XAX ; Exchange Accumulator and X 6A2 19 XABL ; Exchange Accumulator and BL 6A3 7D LDI 2 ; Load Accumulator Immediate 6A4 0D AND ; Logical AND 6A5 1A XAX ; Exchange Accumulator and X 6A6 19 XABL ; Exchange Accumulator and BL 6A7 1A XAX ; Exchange Accumulator and X 6A8 69 ADI 6 ; skip on 2-cycl below 6A9 1C 21 IOL 21 ; Input/Output Long 6AB 17 INCB ; Increment BL 6AC 19 XABL ; Exchange Accumulator and BL 6AD 1A XAX ; Exchange Accumulator and X 6AE 19 XABL ; Exchange Accumulator and BL 6AF 7B LDI 4 ; Load Accumulator Immediate 6B0 0D AND ; Logical AND 6B1 1A XAX ; Exchange Accumulator and X 6B2 19 XABL ; Exchange Accumulator and BL 6B3 1A XAX ; Exchange Accumulator and X 6B4 6B ADI 4 ; skip on 2-cycl below 6B5 1C 21 IOL 21 ; Input/Output Long 6B7 17 INCB ; Increment BL 6B8 19 XABL ; Exchange Accumulator and BL 6B9 1A XAX ; Exchange Accumulator and X 6BA 19 XABL ; Exchange Accumulator and BL 6BB 37 LD 0 ; Load Accumulator from Memory 6BC 1A XAX ; Exchange Accumulator and X 6BD 19 XABL ; Exchange Accumulator and BL 6BE 52 C0 TL 2C0 ; Transfer Long ;general init ;all 2x16 outputs of RIOTs set to 1 ;enable flip flop has not been set yet, since reset 6C0 00 FF LBL 000 ; Load B Long 6C2 70 LDI F ; Load Accumulator Immediate 6C3 1C 21 IOL 21 ; Input/Output Long 6C5 70 LDI F ; Load Accumulator Immediate 6C6 1C 41 IOL 41 ; Input/Output Long 6C8 17 INCB ; Increment BL 6C9 82 T 6C2 ; Transfer 6CA 7F LDI 0 ; Load Accumulator Immediate 6CB 1B LXA ; Load X Register from Accumulator ;turn off A 6CC 1C FB IOL FB ; Input/Output Long ;turn off B 6CE 1C F7 IOL F7 ; Input/Output Long ;16 digits of displays A&B set to 0 6D0 12 LAX ; Load Accumulator from X Register ; loop 0..F->Display Register A (so the displays display sequentially 00000, 11111, 22222, etc... 6D1 1C FE IOL FE ; Input/Output Long 6D3 12 LAX ; Load Accumulator from X Register ; loop 0..F->Display Register B 6D4 1C FD IOL FD ; Input/Output Long 6D6 17 INCB ; Increment BL 6D7 90 T 6D0 ; Transfer ;turn on display 6D8 1C F3 IOL F3 ; Input/Output Long ;jsr delay for ~33 ms*16 ;that is very long, I would say 6000 cyclesx5us*16 or 0.5sec 6DA 01 D2 TML 1D2 ; Transfer and Mark Long 6DC 17 INCB ; Increment BL 6DD 9A T 6DA ; Transfer ;I would say the displays display 00000.. 1111.. 2222.. etc... 6DE 12 LAX ; Load Accumulator from X Register 6DF 6E ADI 1 ; Add Immediate and skip on carry-out 6E0 8B T 6CB ; Transfer 6E1 7F LDI 0 ; Load Accumulator Immediate ;36A display seltest 0 0 0 6E2 03 6A TML 36A ; Transfer and Mark Long ;RAM test. Every location in RAM is written and read with all possible values 0..F 6E4 7F LDI 0 ; Load Accumulator Immediate 6E5 1B LXA ; Load X Register from Accumulator 6E6 18 XBMX ; Exchange BM and X 6E7 70 LDI F ; Load Accumulator Immediate 6E8 1B LXA ; Load X Register from Accumulator 6E9 3F EX 0 ; Exchange Accumulator and Memory 6EA 12 LAX ; Load Accumulator from X Register 6EB 0C EOR ; Logical Exclusive-OR 6EC 1E SKZ ; Skip on Accumulator Zero ;test failed. transfer to 6F9 6ED B9 T 6F9 ; Transfer 6EE 12 LAX ; Load Accumulator from X Register 6EF 60 ADI F ; Add Immediate and skip on carry-out 6F0 B2 T 6F2 ; Transfer 6F1 A8 T 6E8 ; Transfer 6F2 17 INCB ; Increment BL 6F3 A7 T 6E7 ; Transfer 6F4 18 XBMX ; Exchange BM and X 6F5 12 LAX ; Load Accumulator from X Register 6F6 6E ADI 1 ; Add Immediate and skip on carry-out 6F7 A5 T 6E5 ; Transfer 6F8 BA T 6FA ; Transfer ;test failed => FF2 set. 6F9 21 SF2 ; Set FF2 ;test OK ==> FF2 not set 6FA 76 LDI 9 ; Load Accumulator Immediate ;36A display seltest. 9 is main code of test RAM 6FB 03 6A TML 36A ; Transfer and Mark Long 6FD 57 00 TL 700 ; Transfer Long 6FF 00 SET NIB #0 ;routine for checking ports of 11696 ;IOL D0/D8 write/read on Group A ;IOL D1/D9 write/read on Group B ;IOL D2/DA write/read on Group C ;IOL D3/DF write/read on Group D ;IOL D4/DC write/read on Group E ;IOL D5/DD write/read on Group F ;foreach IOL Dwrite(0..15) ;=>makes sure IOLDread reads same value ;36C (alias 778), basically, is a delay of 100ms, and X<-3, B<-001, ; A<-0 because of tml 1D2 which uses @001 for 3rd counter from 7 up to 0 700 03 6C TML 36C ; Transfer and Mark Long 702 1C D0 IOL D0 ; Input/Output Long 704 1C D8 IOL D8 ; Input/Output Long ;TML 1EE call IOL DB from 0..F: reset all in ABCD 706 01 EE TML 1EE ; Transfer and Mark Long 708 82 T 702 ; Transfer 709 1C D1 IOL D1 ; Input/Output Long 70B 1C D9 IOL D9 ; Input/Output Long 70D 01 EE TML 1EE ; Transfer and Mark Long 70F 89 T 709 ; Transfer 710 1C D2 IOL D2 ; Input/Output Long 712 1C DA IOL DA ; Input/Output Long 714 01 EE TML 1EE ; Transfer and Mark Long 716 90 T 710 ; Transfer 717 1C D3 IOL D3 ; Input/Output Long 719 1C DF IOL DF ; Input/Output Long 71B 01 EE TML 1EE ; Transfer and Mark Long 71D 97 T 717 ; Transfer 71E 1C D4 IOL D4 ; Input/Output Long 720 1C DC IOL DC ; Input/Output Long 722 01 FB TML 1FB ; Transfer and Mark Long 724 9E T 71E ; Transfer 725 1C D5 IOL D5 ; Input/Output Long 727 1C DD IOL DD ; Input/Output Long 729 01 FB TML 1FB ; Transfer and Mark Long 72B A5 T 725 ; Transfer 72C 7F LDI 0 ; Load Accumulator Immediate 72D 1C D5 IOL D5 ; Input/Output Long 72F 00 FF LBL 000 ; Load B Long 731 77 LDI 8 ; Load Accumulator Immediate ;36A display seltest. 8 is main code for PIO test 732 03 6A TML 36A ; Transfer and Mark Long ;Beginning of Test IOs of B1/B2 ;/!\ Something to be understood: when we arrive here ;we already have passed the init (namely 6C0 where all IO FF are set to 1 ;then the first IOL 41 here shall return 1 because of that ;C=0 => device 4 is addressed, else device 2 ;FF1==1=> turn 1: set output to 0, and expect to read current state to 1 ;because on entry of this routine all output FF are initialized to 1 ;FF1==0=> turn 2: set output to 1 and expect to read 0, which was put ;there during previous turn of IOL (when FF1 was 1) ;start with RC, SF1, ie device 4, set output to 0, 734 24 RC ; Reset Carry flip-flop 735 B7 T 737 ; Transfer 736 20 SC ; Set Carry flip-flop 737 22 SF1 ; Set FF1 ;set all IOs as output (SES 1) 738 70 LDI F ; 739 1C 20 IOL 20 ; 2 is B2 aka A1762, SES 1: enable all output 73B 70 LDI F ; Load Accumulator Immediate 73C 1C 40 IOL 40 ; 4 is B1 aka A1761, SES 1: enable all output ;goto first test: ;C determine if we address device 4 or 2 ;FF1 determine if we are testing IO for 0 (+5V) or 1 (-12V) 73E 57 44 TL 744 ; Transfer Long 740 57 36 TL 736 ; Transfer Long ;we are doomed, the last test failed (read != written) 742 22 SF1 ; Set FF1 743 9E T 75E ; Transfer ;very first time here C=0 FF1=1: set out to 0 and verify current is 1 744 16 SKF1 ; Skip if FF1 Equals 1 ;we are going to set the current IO to 1 745 77 LDI 8 ; Load Accumulator Immediate ;very first time here (C=0, F1=1) ;we are going to set the current IO to 0 746 7B LDI 4 ; Load Accumulator Immediate 747 1B LXA ; Load X Register from Accumulator ;store 8 or 4 into BM which will be a parameter for the display routine 748 18 XBMX ; Exchange BM and X BM will contain 4 or 8 and will be used in case of failure as param for code display 749 15 SKC ; very first time (vft): no skip because C=0 ;depending on C, we will address IOs of B1 or B2 74A 8E T 74E ; Transfer test B1 74B 1C 21 IOL 21 ; test B2 74D 90 T 750 ; Transfer 74E 1C 41 IOL 41 ; on vft Acc->4, Acc<-1xxx ; because IO F/F0 was initialised to 1 (6C0) 750 16 SKF1 ; Skip if FF1 Equals 1. SKIP on vft 751 66 ADI 9 ; Add Immediate and skip on carry-out, execute this only on 1st turn (FF1=1) 752 66 ADI 9 ; on vft A<-A+9 with A=1xxx=>skip ; but on 2nd turn (FF1=0), we expect ; output is 0 as it was set during first turn ; if it is 0, no skip on the first ADI, ; hence skip on the 2nd ADI, outp is OK ; if it is 1, it is not normal and it will skip ; on the first ADI, skipping the 2nd ADI, ; landing at the error routine call ;T 742: the ouput is not read as it was written at t-1=>display io error, BM:error type, BL: #IO, A: #device ;the simulator should reply b1xxx when FF1==1, or b0000 when FF1=0 753 82 T 742 ; Transfer to display error. BL contains the erroneous IO 754 17 INCB ; ;select next #IO and loop back 755 84 T 744 ; Transfer to next IO test ;all IOs tested ;if both voltage level were checked 756 16 SKF1 ; Skip if current turn is turn 1, go ahead with turn 2 757 9A T 75A ; Transfer ;start again with other polarity test 758 26 RF1 ; Reset FF1, to indicate start of turn2 759 84 T 744 ; Transfer to entry loop for turn 2 ;start again with the other device or we are done 75A 15 SKC ; Skip on Carry flip-flop, we are done 75B 80 T 740 ; rexecute test turn 1, 2 for device B2 ;everything went well... ;/!\ but it is not possible to go well ;because IO15 of B2 is permanently tied to +5V ;(thank you Ralf, for this one) ;hence the display is 2.4.. for B2 IO#F failed 75C 00 FF LBL 000 ; Load B Long ;There are 2 ways to reach 75E: 1/everything went well, 2/a test failed from 742 ;select #device causing failure, or 2 if all ok 75E 15 SKC ; Skip on Carry flip-flop 75F 7E LDI 1 ; Load Accumulator Immediate 760 7D LDI 2 ; Acc<-2 when all tests passed ;36A display seltest (act. 78D) 761 03 6A TML 36A ; Transfer and Mark Long ;most probably play short tone ;as mentionned in the operator manual p3.3, middle line 763 70 LDI F ; Load Accumulator Immediate 764 1C D3 IOL D3 ; Input/Output Long 766 01 D2 TML 1D2 ; Transfer and Mark Long 768 7F LDI 0 ; Load Accumulator Immediate 769 1C D3 IOL D3 ; Input/Output Long ;goto next test (open or short of coils) 76B 57 C0 TL 7C0 ; Transfer Long 76D 1A XAX ; Exchange Accumulator and X 76E 18 XBMX ; Exchange BM and X 76F 21 SF2 ; Set FF2 770 57 32 TL 732 ; Transfer Long ;landed here from end of 1EE, with BM=1 and A from before 1EE call ;if A==0 772 0C EOR ; Logical Exclusive-OR 773 1E SKZ ; Skip on Accumulator Zero 774 AD T 76D ; Transfer 775 17 INCB ; Increment BL ;goto 77C if A==0 (which caused BL++) 776 BC T 77C ; Transfer 777 BC T 77C ; Transfer ;jsr 778 is wait 100ms, and rtn (A=1, X=3, B=001) ;landed here from 36C, called from a TML ;A<-#1, X<-#3 778 7C LDI 3 ; Load Accumulator Immediate 779 1B LXA ; Load X Register from Accumulator 77A 00 FE LBL 001 ; Load B Long 77C 11 LABL ; Load Accumulator with BL ; ;A<-mem(@001), BL<-#1, mem(@001)<-#1 if came from 778 77D 3F EX 0 ; Exchange Accumulator and Memory ;tempox3==>about 100ms 77E 57 80 TL 780 ; we are at a page frontier. Manage it 780 01 D2 TML 1D2 ; Transfer and Mark Long 782 01 D2 TML 1D2 ; Transfer and Mark Long 784 01 D2 TML 1D2 ; Transfer and Mark Long ;A<-mem(@001) which is #0 on TML 1D2 exit... ?? 786 37 LD 0 ; Load Accumulator from Memory ;skip if BL==#0 (which is false at entry from 778) 787 40 SKBI 0 ; Skip if BL equals to Immediate. 788 05 RTN ; Return A<-#1, X<-#3, BL<-#1 ;here at first entry from 778, we have: ;X=3, A=1 789 1A XAX ; Exchange Accumulator and X ;A<-A+1, that is 4 at first entry from 778 78A 6E ADI 1 ; Add Immediate and skip on carry-out 78B 1A XAX ; Exchange Accumulator and X 78C 07 RTNSK ; Return and Skip with A<-#4, X<-#3 ;this routine displays on player 2 : ... ;A was loaded test number ;BM, BL were loaded with something (subparam of test?) ;probably display test number x (x in A) ;Also FF1 is used for doubling the time on display, and FF2 for doubling one more time 78D 1B LXA ; Load X Register from Accumulator ;KAF: turn off display A 78E 1C FB IOL FB ; Input/Output Long 790 12 LAX ; Load Accumulator from X Register ;KLA: loads digit 1 of display #A with A ;KLA returns F I guess, then 2nd KLA load blank 791 1C FE IOL FE ; Input/Output Long 793 1C FE IOL FE ; Input/Output Long ;KLA: loads digit 3 of display #A with BM ;KLA returns f I guess, then 2nd KLA load blank 795 18 XBMX ; BM<-X, which act. is Acc arg. X<-BM 796 12 LAX ; A<-X<-BM 797 1C FE IOL FE ; Input/Output Long 799 1C FE IOL FE ; Input/Output Long ;KLA: load digit 5 of display #A with BL 79B 11 LABL ; Load Accumulator with BL 79C 1C FE IOL FE ; Input/Output Long 79E 18 XBMX ; X is restored with initial value of A ; then 11 blanks displayed (16-5) (the rest of unused digits) 79F 7A LDI 5 ; Load Accumulator Immediate 7A0 19 XABL ; Exchange Accumulator and BL 7A1 70 LDI F ; Load Accumulator Immediate 7A2 1C FE IOL FE ; Input/Output Long 7A4 17 INCB ; Increment BL from 5 to 16 7A5 A2 T 7A2 ; loop ;KDN Turn On display 7A6 1C F3 IOL F3 ; Input/Output Long ;delay for (16)*33ms 2 times if FF1=1 7A8 01 D2 TML 1D2 ; Transfer and Mark Long 7AA 17 INCB ; Increment BL 7AB A8 T 7A8 ; Transfer 7AC 16 SKF1 ; Skip if FF1 Equals 1 ;end of tempo goto 7B0 7AD B0 T 7B0 ; Transfer 7AE 26 RF1 ; Reset FF1 7AF A8 T 7A8 ; Transfer ;KAF: turn off display A 7B0 1C FB IOL FB ; Input/Output Long 7B2 01 D2 TML 1D2 ; Transfer and Mark Long 7B4 17 INCB ; Increment BL 7B5 B2 T 7B2 ; Transfer 7B6 14 SKF2 ; Skip if FF2 Equals 1 7B7 05 RTN ; Return 7B8 A6 T 7A6 ; Transfer 7B9 22 SF1 ; Set FF1 7BA 19 XABL ; Exchange Accumulator and BL 7BB 12 LAX ; Load Accumulator from X Register ;36A display seltest 7BC 03 6A TML 36A ; Transfer and Mark Long 7BE 57 D1 TL 7D1 ; Transfer Long 7C0 03 6E TML 36E ; coils selftest against sc/oc 7C2 72 LDI D ; Load Accumulator Immediate 7C3 09 ADSK ; Add and skip on carry-out 7C4 9B T 7DB ; Transfer 7C5 1B LXA ; Load X Register from Accumulator 7C6 1C D6 IOL D6 ; Input/Output Long 7C8 03 6E TML 36E ; coils selftest against sc/oc 7CA 12 LAX ; Load Accumulator from X Register 7CB 1C DB IOL DB ; Input/Output Long 7CD 7E LDI 1 ; Load Accumulator Immediate 7CE 0C EOR ; Logical Exclusive-OR 7CF 1E SKZ ; Skip on Accumulator Zero 7D0 A0 T 7E0 ; Transfer 7D1 12 LAX ; Load Accumulator from X Register 7D2 6E ADI 1 ; Add Immediate and skip on carry-out 7D3 85 T 7C5 ; Transfer 7D4 00 FF LBL 000 ; Load B Long 7D6 7C LDI 3 ; Load Accumulator Immediate ;36A display seltest display 3.0.0. 7D7 03 6A TML 36A ; Transfer and Mark Long ; test cmosram and write it to ram 7D9 55 10 TL 510 ; goto test ram cmos 7DB 21 SF2 ; Set FF2 7DC 37 LD 0 ; Load Accumulator from Memory 7DD 1E SKZ ; Skip on Accumulator Zero 7DE A5 T 7E5 ; Transfer 7DF A6 T 7E6 ; Transfer 7E0 37 LD 0 ; Load Accumulator from Memory 7E1 1E SKZ ; Skip on Accumulator Zero 7E2 A7 T 7E7 ; Transfer 7E3 21 SF2 ; Set FF2 7E4 7B LDI 4 ; Load Accumulator Immediate 7E5 7A LDI 5 ; Load Accumulator Immediate 7E6 79 LDI 6 ; Load Accumulator Immediate 7E7 78 LDI 7 ; Load Accumulator Immediate 7E8 57 B9 TL 7B9 ; Transfer Long ;BL<-X ;probably self test of shorts and open for coils ;Sys3 uses a 11660 (pps-4/2) implying that X is sent to DIO when DOA is performed ;but on the schematic, one can see that DIO is pulled down to-12V ==> not used 7EA 12 LAX ; Load Accumulator from X Register 7EB 19 XABL ; Exchange Accumulator and BL 7EC 77 LDI 8 ; Load Accumulator Immediate 7ED 1B LXA ; Load X Register from Accumulator ;A is the number for reading SC (short-circuits) and OC ;To be confirmed 7EE 75 LDI A ; Load Accumulator Immediate 7EF 1D DOA ; Discrete Output ;delay 33ms more probably wait for a coil to consume or not and letting fall power play voltage) 7F0 01 D2 TML 1D2 ; Transfer and Mark Long 7F2 27 DIA ; Discrete Input Group A 7F3 3F EX 0 ; save returns at t 7F4 0C EOR ; Logical Exclusive-OR 7F5 1E SKZ ; Skip on Accumulator Zero 7F6 AC T 7EC ; there is change in the returns of the matrix at t since t-1 ; will loop on the reading until reply is stabilized ;the return for DOA #A can be: ;0011: 2.4.6 or X.4.4 (no voltage or short) ;0010: 2.4.5 or . . . (normal consumption) ;0001: faulty reading ;0010: X.4.7 (no consumption - Open) 7F7 12 LAX ; Load Accumulator from X Register 7F8 6E ADI 1 ; Add Immediate and skip on carry-out 7F9 AD T 7ED ; Transfer 7FA 11 LABL ; Load Accumulator with BL 7FB 1A XAX ; Exchange Accumulator and X 7FC 7C LDI 3 ; Load Accumulator Immediate 7FD 0D AND ; Logical AND 7FE 3F EX 0 ; Exchange Accumulator and Memory 7FF 05 RTN ; Return ;beginning of game eprom (here it is screech) 800 C7 LB (C7) (B<=0E0) ;(target addr=149): bit reset in memory at @(B reg) only if FF1 is 1 801 DC TM (DC) ;(target addr=149) 802 21 SF2 803 C0 LB (C0) (B<=048) 804 78 LDI 7 805 0D AND 806 64 ADI B 807 8A T 80A 808 52 D0 TL 2D0 80A CF LB (CF) (B<=017) 80B 77 LDI 8 80C 7F LDI 0 80D 2F EXD 0 80E 8C T 80C ;something with play signal 80F 77 LDI 8 810 1C D5 IOL D5 ;RF1, and jsr 005 812 01 03 TML 103 ; Transfer and Mark Long 814 7C LDI 3 ; Load Accumulator Immediate 815 1C D0 IOL D0 ; Input/Output Long ;delay 33ms 817 01 D2 TML 1D2 ; Transfer and Mark Long ;restart prog. 819 52 F4 TL 2F4 ; Transfer RAM to HM6508 and restart 81B 26 RF1 ; Reset FF1 81C 00 EC LBL 013 ; Load B Long 81E 73 LDI C ; Load Accumulator Immediate 81F 01 95 TML 195 ; Transfer and Mark Long 821 B1 T 831 ; Transfer 822 F6 TM (F6) (target addr=193) ; Transfer and Mark Indirect 823 D7 TM (D7) (target addr=15C) ; Transfer and Mark Indirect 824 16 SKF1 ; Skip if FF1 Equals 1 825 AC T 82C ; Transfer 826 B2 T 832 ; Transfer 827 77 LDI 8 ; Load Accumulator Immediate 828 7B LDI 4 ; Load Accumulator Immediate 829 C6 LB (C6) (B<=015) 82A 0D AND 82B 1E SKZ 82C FB TM (FB) ;(target addr=1AC) 82D B3 T 833 82E 00 EB LBL 014 ; Load B Long 830 F7 TM (F7) (target addr=194) ; Transfer and Mark Indirect 831 7A LDI 5 ; Load Accumulator Immediate 832 78 LDI 7 ; Load Accumulator Immediate 833 79 LDI 6 ; Load Accumulator Immediate 834 7F LDI 0 ; Load Accumulator Immediate 835 22 SF1 ; Set FF1 836 58 4E TL 84E ; Transfer Long 838 00 EB LBL 014 ; Load B Long 83A D9 TM (D9) (target addr=141) ; Transfer and Mark Indirect 83B B1 T 831 ; Transfer 83C 22 SF1 ; Set FF1 83D 25 RF2 ; Reset FF2 83E 54 C2 TL 4C2 ; Transfer Long 840 CE LB (CE) (B<=016) 841 D6 TM (D6) ;(target addr=17B) 842 84 T 844 843 8D T 84D 844 00 EB LBL 014 846 F5 TM (F5) ;(target addr=192) 847 7C LDI 3 848 70 LDI F 849 F9 TM (F9) (target addr=1B5) ; Transfer and Mark Indirect ;RF1, and jsr 005 84A 01 03 TML 103 ; Transfer and Mark Long 84C 80 T 840 ; Transfer 84D 79 LDI 6 ; Load Accumulator Immediate 84E F9 TM (F9) (target addr=1B5) ; Transfer and Mark Indirect 84F C7 LB (C7) (B<=0E0) 850 DC TM (DC) ;(target addr=149) 851 F8 TM (F8) ;(target addr=199) 852 95 T 855 853 51 0E TL 10E ; Transfer Long ;something with play signal (IO24) 855 77 LDI 8 ; Load Accumulator Immediate 856 1C D5 IOL D5 ; Input/Output Long 858 73 LDI C ; Load Accumulator Immediate 859 1C D0 IOL D0 ; Input/Output Long 85B 93 T 853 ; Transfer ;coil #8 or coil #9 85C 76 LDI 9 ; Load Accumulator Immediate 85D 77 LDI 8 ; Load Accumulator Immediate 85E 1C D6 IOL D6 ; Input/Output Long 860 CE LB (CE) (B<=016) 861 D2 TM (D2) ;(target addr=122) 862 A5 T 865 863 75 LDI A 864 3F EX 0 ; Exchange Accumulator and Memory 865 7E LDI 1 ; Load Accumulator Immediate 866 7A LDI 5 ; Load Accumulator Immediate 867 58 35 TL 835 ; Transfer Long 869 0F OR ; Logical OR 86A 3F EX 0 ; Exchange Accumulator and Memory 86B 1E SKZ ; Skip on Accumulator Zero ;bit b1000 set in memory at @(B reg) only if FF1 is 1 86C DB TM (DB) (target addr=143) ; set bit 1000b of current ram nibble 86D 93 T 853 ; Transfer 86E 00 EC LBL 013 ; Load B Long 870 73 LDI C ; Load Accumulator Immediate 871 01 95 TML 195 ; Transfer and Mark Long 873 B7 T 877 ; Transfer 874 16 SKF1 ; Skip if FF1 Equals 1 875 7C LDI 3 ; Load Accumulator Immediate 876 73 LDI C ; Load Accumulator Immediate 877 0C EOR ; Logical Exclusive-OR 878 3F EX 0 ; Exchange Accumulator and Memory 879 43 SKBI 3 ; Skip if BL equals to Immediate. 87A AE T 86E ; Transfer 87B 16 SKF1 ; Skip if FF1 Equals 1 87C A6 T 866 ; Transfer 87D 26 RF1 ; Reset FF1 87E 7C LDI 3 ; Load Accumulator Immediate 87F B1 T 871 ; Transfer 880 54 56 TL 456 ; Transfer Long 882 83 T 883 ; Transfer 883 7E LDI 1 ; Load Accumulator Immediate 884 7D LDI 2 ; Load Accumulator Immediate 885 C6 LB (C6) (B<=015) 886 58 69 TL 869 888 58 DB TL 8DB 88A 58 DB TL 8DB 88C 58 5D TL 85D ; Transfer Long 88E 58 27 TL 827 ; Transfer Long 890 58 EF TL 8EF ; Transfer Long 892 58 C7 TL 8C7 ; Transfer Long 894 58 C8 TL 8C8 ; Transfer Long 896 58 2E TL 82E ; Transfer Long 898 58 DE TL 8DE ; Transfer Long 89A 58 DE TL 8DE ; Transfer Long 89C 58 5C TL 85C ; Transfer Long 89E 58 28 TL 828 ; Transfer Long 8A0 58 40 TL 840 ; Transfer Long 8A2 58 34 TL 834 ; Transfer Long 8A4 58 1B TL 81B ; Transfer Long 8A6 58 1C TL 81C ; Transfer Long 8A8 58 E4 TL 8E4 ; Transfer Long 8AA 58 E4 TL 8E4 ; Transfer Long 8AC 58 3C TL 83C ; Transfer Long 8AE 7E LDI 1 ; Load Accumulator Immediate 8AF 7D LDI 2 ; Load Accumulator Immediate 8B0 58 CB TL 8CB ; Transfer Long 8B2 C6 LB (C6) (B<=015) 8B3 58 70 TL 870 8B5 05 RTN 8B6 58 2D TL 82D ; Transfer Long 8B8 58 E1 TL 8E1 ; Transfer Long 8BA 58 E1 TL 8E1 ; Transfer Long 8BC 58 38 TL 838 ; Transfer Long 8BE AF T 8AF ; Transfer 8BF 05 RTN ; Return 8C0 7F LDI 0 ; Load Accumulator Immediate 8C1 1C 41 IOL 41 ; Input/Output Long 8C3 17 INCB ; Increment BL 8C4 80 T 8C0 ; Transfer 8C5 52 DB TL 2DB ; Transfer Long 8C7 7E LDI 1 ; Load Accumulator Immediate 8C8 7D LDI 2 ; Load Accumulator Immediate 8C9 00 EC LBL 013 ; Load B Long 8CB C6 LB (C6) (B<=015) 8CC 0D AND 8CD 1E SKZ 8CE FF TM (FF) ;(target addr=1AE) 8CF B4 T 8F4 ; Transfer ;jump here from 1B9 8D0 00 1A LBL 0E5 ; Load B Long 8D2 0D AND ; Logical AND 8D3 1F DECB ; Decrement BL 8D4 0D AND ; Logical AND 8D5 00 EB LBL 014 ; Load B Long 8D7 1E SKZ ; Skip on Accumulator Zero 8D8 05 RTN ; Return 8D9 26 RF1 ; Reset FF1 8DA 05 RTN ; Return 8DB 7E LDI 1 ; Load Accumulator Immediate 8DC FD TM (FD) (target addr=1B9) ; Transfer and Mark Indirect 8DD D9 TM (D9) (target addr=141) ; Transfer and Mark Indirect 8DE 7D LDI 2 ; Load Accumulator Immediate 8DF FD TM (FD) (target addr=1B9) ; Transfer and Mark Indirect ;bit 0100 set in memory at @(B reg) only if FF1 is 1 8E0 DA TM (DA) (target addr=142) ; Transfer and Mark Indirect 8E1 77 LDI 8 ; Load Accumulator Immediate 8E2 FD TM (FD) (target addr=1B9) ; Transfer and Mark Indirect ;bit b1000 set in memory at @(B reg) only if FF1 is 1 8E3 DB TM (DB) (target addr=143) ; set bit 1000b of current ram nibble 8E4 7B LDI 4 ; Load Accumulator Immediate 8E5 FD TM (FD) (target addr=1B9) ; Transfer and Mark Indirect 8E6 1F DECB ; Decrement BL 8E7 DC TM (DC) (target addr=149) ; Transfer and Mark Indirect 8E8 D9 TM (D9) (target addr=141) ; Transfer and Mark Indirect 8E9 17 INCB ; Increment BL 8EA E7 TM (E7) (target addr=154) ; Transfer and Mark Indirect 8EB 1F DECB ; Decrement BL 8EC DE TM (DE) (target addr=14B) ; Transfer and Mark Indirect ;bit b1000 set in memory at @(B reg) only if FF1 is 1 8ED DB TM (DB) (target addr=143) ; set bit 1000b of current ram nibble 8EE B4 T 8F4 ; Transfer 8EF 00 EB LBL 014 ; Load B Long 8F1 F6 TM (F6) (target addr=193) ; Transfer and Mark Indirect 8F2 B6 T 8F6 ; Transfer 8F3 FF TM (FF) (target addr=1AE) ; Transfer and Mark Indirect 8F4 58 33 TL 833 ; Transfer Long 8F6 58 32 TL 832 ; Transfer Long 8F8 50 11 TL 011 ; Transfer Long 8FA 58 4F TL 84F ; Transfer Long 8FC C0 LB (C0) (B<=048) 8FD 80 T 8C0 8FE 52 1E TL 21E