LB
Load B Indirect
2cy.
Sixteen consecutive locations on ROM
page 3 (I2) contain data which
can be loaded into the eight
least significant bits of the B
register by use of any LB instruction.
The four most significant bits of B register
will be loaded with zeroes.
The contents of the SB register will be
destroyed. This instruction takes two
cycles to execute but occupies only one ROM
word. (Automatic return)
SB<-SA
SA<-P
P(12:5)<-00001100
P(4:1)<-I1(4:1)
BU<-0000
B(8:1)<-|I2(8:1)|
P<-SA
SA<->SB
LBL
Load B Long
2cy.
This instruction occupies two ROM words,
the second of which will be loaded
into the eight least significant
bits of the B register.
The four most significant bits of B (BU)
will be loaded with zeroes.
BU<-0000
B(8:1)<-|I2(8:1)|
CYS
Cycle SA register and Accumulator
1cy.
A 4-bit right shift of the SA
register takes place with the four
bits which are shifted off the end of SA
being transferred into the accumulator.
The contents of the accumulator are
placed in the left end of SA register.
A<-/SA(4:1)
SA(4:1)<-SA(8:5)
SA(8:5)<-SA(12:9)
SA(12:9)<-/A
SAG
Special Address Generation
1cy.
This instruction causes the eight most
significant bits of the RAM address output
to be zeroed during the next cycle only.
Note that this instruction does not
alter the contents of the B register.
A/B Bus(12:5)<-0000 0000
A/B Bus(4:1)<-BL(4:1)
Contents of 'B' remain unchanged
LABL
Load Accumulator with BL
1cy.
The contents of BL register are
transferred to the Accumulator.
A<-BL
LD
Load Accumulator from Memory
1cy.
The 4-bit contents of RAM currently
addressed by B register are placed in
the accumulator. The RAM address in
the B register is then modified
by the result of an exclusive OR
of the 3-bit immediate field
I(3:1) and B(7:5).
A<-M
B(7:5)<-B(7:5)xor|I(3:1)|
INCB
Increment BL
1cy.
BL register (least significant four bits of B register)
is incremented by 1. If the new contents of BL
is 0000, then the next ROM word will be ignored.
BL<-BL+1
Skip on BL=0000
DECB
Decrement BL
1cy.
BL register (least significant four bits of B register)
is decremented by 1. If the new contents of BL
is 1111, then the next ROM word will be ignored.
BL<-BL-1
Skip on BL=1111
RTN
Return
1cy.
This instruction executes a return
from subroutine by loading contents of
SA register into P register and interchange
the SB and SA registers.
P<-SA
SA<->SB
RTNSK
Return and Skip
1cy.
Same as RTN except the first ROM
word encountered after the return
from subroutine is skipped.
P<-SA
SA<->SB
P<-P+1
XS
Exchange SA and SB
1cy.
The 12-bit contents of SA register and SB
register are exchanged
SA<->SB
AD
Add
1cy.
The result of binary addition
of contents of accumulator
and 4-bit contents of the RAM currently
addressed by B register, replaces the
contents of accumulator. The resulting
carry-out is loaded into C flip-flop.
C,A<-A+M
ADC
Add with carry-in
1cy.
Same as AD except the
C flip-flop serves as a carry-in
to the adder.
C,A<-A+M+C
ADCSK
Add with carry-in and skip on carry-out
1cy.
Same as ADSK except the
C flip-flop serves as a carry-in
to the adder.
C,A<-A+M+C
Skip if C=1
ADSK
Add and skip on carry-out
1cy.
Same as AD except the next ROM word
will be skipped (ignored) if
a carry-out is generated.
C,A<-A+M
Skip if C=1
AND
Logical AND
1cy.
The result of logical AND
of accumulator and 4-bit contents
of RAM currently addressed by B register
replaces contents of accumulator.
A<-A&M
OR
Logical OR
1cy.
The result of logic OR
of accumulator and 4-bit contents
of RAM currently addressed by B register
replaces contents of accumulator.
A<-A|M
EOR
Logical Exclusive-OR
1cy.
The result of logic Exclusive-OR
of accumulator and 4-bit contents
of RAM currently addressed by B register
replaces contents of accumulator.
A<-A^M
COMP
Complement
1cy.
Each bit of the accumulator is logically
complemented and placed in the accumulator.
A<-~A
XABL
Exchange Accumulator and BL
1cy.
The contents of accumulator and BL register
are exchanged.
A<->BL
LBUA
Load BU with A
1cy.
The contents of accumulator are
transferred to BU register.
Also, the contents of currently
addressed RAM are transferred to
accumulator.
BU<-A
A<-M
LBMX
Load BM with X
1cy.
The contents of X register are
transferred to BM register.
BM<-X
XBMX
Exchange BM and X
1cy.
The contents of BM register and X
register are exchanged
X<->BM
XAX
Exchange Accumulator and X
1cy.
The contents of accumulator and X
register are exchanged
X<->A
LAX
Load Accumulator from X Register
1cy.
The 4-bit contents of the X register
are placed in the accumulator.
A<-X
LXA
Load X Register from Accumulator
1cy.
The contents of the accumulator
are transferred to the X register.
X<-A
DIA
Discrete Input Group A
1cy.
Data at the inputs to discrete:
Group A is transferred to the accumulator.
A<-DIA
DIB
Discrete Input Group B
1cy.
Data at the inputs to discrete:
Group B is transferred to the accumulator.
A<-DIB
DOA
Discrete Output
1cy.
The contents of the accumulator
are transferred to the discrete output register.
DOA<-A
IOL
Input/Output Long
2cy.
This instruction occupies two ROM
words and requires two cycles for
execution. The first ROM word is
I/O Enable signal.
The second ROM word is then received by the I/O
devices and decoded for address and command.
The contents of the accumulator inverted
are placed on the data lines for acceptance
by the I/O. At the same time, input
data received by the I/O device
is transferred to the accumulator inverted.
/A->Data Bus
A<-/Data Bus
I2->I/O Device
T
Transfer
1cy.
An unconditional transfer to a ROM word
on the current page takes place. The least
significant 6-bits of P register P(6:1)
are replaced by six bit immediate field
I(6:1)
P(6:1)<-I(6:1)
TL
Transfer Long
2cy.
This instruction executes a transfer to any ROM
word on any page. It occupies two ROM words and
requires two cycles for execution.
The first byte loads P(12:9) with field
I1(4:1) and then the second byte I2(8:1) is
placed in P(8:1)
P(12:9)<-I1(4:1)
P(8:1)<-I2(8:1)
TML
Transfer and Mark Long
2cy.
This instruction executes a transfer and
mark to any location on ROM page
4 through 15. It occupies two ROM words
and requires two cycle times for execution.
SB<-SA
SA<-P
P(12:9)<-I1(4:1)
P(8:1)<-I2(8:1)
TM
Transfer and Mark Indirect
2cy.
48 consecutive locations on ROM page 3
contains pointer data which identify
subroutine entry addresses.
These subroutine entry addresses are
limited to pages 4 through 7.
This TM instruction will save the
address of the next ROM word in
the SA register after loading
the original contents of SA into SB.
A transfer then occurs to one of the subroutine
entry addresses. This instruction occupies
one ROM word but takes two cycles for
execution.
SB<-SA
SA<-P
P(12:7)<-000011
P(6:1)<-I1(8:1)
P(12:9)<-0001
P(8:1)<-I2(8:1)
LDI
Load Accumulator Immediate
1cy.
The 4-bit contents, immediate field I[4:1],
of the instruction are placed in accumulator.
A<-|I(4:1)|
ADI
Add Immediate and skip on carry-out
1cy.
The result of binary addition of contents
of accumulator and 4-bit immediate
field of instruction word replaces the contents
of accumulator. The next ROM word will be
skipped (ignored) if a carry-out
is generated. This instruction does not
use or change the C flip-flop.
The immediate field I(4:1)
of this instruction may not be equal to
binary 0000 or 1010 (See CYS and DC)
A<-A+|I(4:1)|
Skip if carry-out=one
I(4:1)!=0000
I(4:1)!=1010
DC
Decimal Correction
1cy.
Binary 1010 is added to contents
of accumulator. Result is stored in accumulator.
Instruction does not use or change
carry flip-flop or skip.
A<-A+|I(4:1)|
Skip if carry-out=one
I(4:1)!=0000
I(4:1)!=1010
SKZ
Skip on Accumulator Zero
1cy.
The next ROM word will be ignored if
accumulator is 0.
skip if A=0000
SKF2
Skip if FF2 Equals 1
1cy.
The next ROM word will be ignored if
FF2 is 1.
skip if FF2=1
SKF1
Skip if FF1 Equals 1
1cy.
The next ROM word will be ignored if
FF1 is 1.
skip if FF1=1
SKC
Skip on Carry flip-flop
1cy.
The next ROM word will be ignored if
C flip-flop is 1.
skip if C=1
SKBI
Skip if BL equals to Immediate.
1cy.
The next ROM word will be ignored if
the the least significant four
bits of B register (BL) is equal
to the 4-bit immediate field
I(4:1) of instruction.
skip if BL=I(4:1)
RF1
Reset FF1
1cy.
Flip-flop 1 is set to 0.
FF1<-0
SF1
Set FF1
1cy.
Flip-flop 1 is set to 1.
FF1<-1
SF2
Set FF2
1cy.
Flip-flop 2 is set to 1.
FF2<-1
SC
Set Carry flip-flop
1cy.
The C Flip-flop is set to 1.
C<-1
RC
Reset Carry flip-flop
1cy.
The C Flip-flop is set to 0.
C<-0
RF2
Reset FF2
1cy.
Flip-flop 2 is set to 0.
FF2<-0
EXD
Exchange Accumulator and Memory and decrement BL
1cy.
Same as EX except RAM address in B register
is further modified by decrementing BL by 1.
If the new contents of BL is 1111, the next
ROM word will be ignored
A<->M
B(7:5)<-B(7:5)xor|I(3:1)|
BL<-BL-1
skip on BL=1111
EX
Exchange Accumulator and Memory
1cy.
Same as LD except the contents of accumulator
are also placed in currently addressed RAM location.
A<->M
B(7:5)<-B(7:5)xor|I(3:1)|
Notes:
Only the first occurrence of an LDI in a consecutive string of LDI's will be executed.
The program will ignore the remaining LDI's and execute next valid instruction.
Only the first occurrence of an LB or LBL instruction in a consecutive string of LB or LBL will be executed.
The program will ignore the remaining LB or LBL and execute next valid instruction.
Within subroutines the LB instruction must be used with caution because the contents of SB have been modified.
DOA has got additional features on PPS-4/2 compared to PPS-4.
FAQ for borderline cases:
What about a string of mixed LB and LBL?
In the datasheet, the formulation Only the first occurrence of an LB or LBL instruction in a consecutive string of LB or LBL will be executed is rather imprecise.
What is to be understood if both instructions are mixed together:
LBL 0x36
LB (0xC0)
LBL 0x37
The answer is: Only the first LBL will be executed. LB will be ignored, as the second LBL.
What about a 2-cycle instruction just after a skip instruction?
Skip instructions such as SKZ, SKF1, ADI, etc... have a skip condition, where the next word is ignored (executed as a NOP).
OK that's easy in constructions such as:
05C 09 ADSK ; Add and skip on carry-out
05D AC T 06C ; Transfer
05E 1A XAX ; Exchange Accumulator and X
If the skip condition is met, the transfer instruction is read, but not executed,
and then the program continues with XAX...
But let's imagine the following:
05C 09 ADSK ; Add and skip on carry-out
05D 50 11 TL 011 ; Transfer Long (but in a sense, 0x11 is also LABL...)
05F 1A XAX ; Exchange Accumulator and X
What is going to happen here?
If the skip condition is met, then next word (i.e. 0x50) is read and ignored, and finally the
next executed instruction will be Ox11 (LABL).
What exactly does CYS?
In the datasheet, there is a discrepancy between the comments and the equation. The comment reads
that "Cycle SA register and Accumulator", but the equation is weird and writes
A<-SA(4:1)\nSA(4:1)<-SA(8:5)\nSA(8:5)<-SA(12:9)\nSA(12:9)<-/A
Would not it be a missing / in A<-SA? Or a typo in the end?
The answer is yes there is a typo. The correct equation is as follows:
A<-/SA(4:1)\nSA(4:1)<-SA(8:5)\nSA(8:5)<-SA(12:9)\nSA(12:9)<-/A
How does work the PC?
The PC is a 12-bit register. It is actually composed of 2x6-bit sub-registers:
PC_hi(12:7)
PC_lo(6:1)
What is to be understood here, is that only PC_lo is a counter, while PC_hi is immutable,
except from TL and TML instructions.
Hence, a code full of zeros from 0 to FFF, for example, will not run from 0 to FFF doing nothing,
but only from 0 to 0x3F, and then will loop to 0. This detail might be important in several cases.
How do we know all this things?
Actually, we were not sure about all the previous situations. Therefore, we made the following pps4
program barocco.as.
You will see in the trace (added in the end of the file) how a real 11696 CPU handles this cases.
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